Looks like a pci express connector. PCI Express - what is it and the main characteristics

In this article, we will discuss the reasons for the success of the PCI bus and describe the high-performance technology that is replacing it - the PCI Express bus. We will also consider the history of development, hardware and software levels of the PCI Express bus, features of its implementation and list its advantages.

When in the early 1990s. when it appeared, its technical characteristics significantly surpassed all buses that existed until that time, such as ISA, EISA, MCA and VL-bus. At that time, the PCI (Peripheral Component Interconnect) bus, which ran at 33 MHz, was well suited for most peripheral devices. But today the situation has changed in many ways. First of all, the clock speeds of the processor and memory have increased significantly. For example, processor clock speeds have increased from 33 MHz to several GHz, while the PCI operating frequency has increased to only 66 MHz. The emergence of technologies such as Gigabit Ethernet and IEEE 1394B threatened that all PCI bus bandwidth could be spent on servicing a single device based on these technologies.

At the same time, the PCI architecture has a number of advantages over its predecessors, so it was irrational to completely revise it. First of all, it does not depend on the type of processor, it supports buffer isolation, bus mastering technology and PnP technology in full. Buffer isolation means that the PCI bus operates independently of the internal processor bus, which allows the processor bus to function independently of the speed and load of the system bus. With bus hijacking technology, peripherals can directly control the transfer of data on the bus, instead of waiting for help from the central processor, which would affect system performance. Finally, Plug and Play support allows for automatic configuration and configuration of devices using it and avoids the hassle of jumpers and switches, which pretty much ruined the lives of owners of ISA devices.

Despite the undoubted success of PCI, it faces serious problems at the present time. These include limited bandwidth, lack of real-time data transfer capabilities, and lack of support for next-generation networking technologies.

Comparative characteristics of various PCI standards

It should be noted that the actual throughput may be less than the theoretical one due to the principle of the protocol and the peculiarities of the bus topology. In addition, the total bandwidth is shared among all devices connected to it, so the more devices sit on the bus, the less bandwidth each of them gets.

Improvements to the standard such as PCI-X and AGP were designed to eliminate its main drawback - low clock speed. However, an increase in the clock frequency in these implementations entailed a decrease in the effective bus length and the number of connectors.

The new generation of the bus - PCI Express (or PCI-E for short), was first introduced in 2004 and was intended to solve all the problems faced by its predecessor. Most new computers today are equipped with PCI Express. Although standard PCI slots are also present in them, the time is not far off when the bus will become history.

PCI Express architecture

The bus architecture has a layered structure, as shown in the figure.

The bus supports the PCI addressing model, which allows all currently existing drivers and applications to work with it. In addition, the PCI Express bus uses the standard PnP mechanism provided by the previous standard.

Consider the purpose of the various levels of PCI-E organization. At the program level of the bus, read / write requests are formed, which are transmitted at the transport level using a special packet protocol. The data layer is responsible for error-correcting coding and ensures data integrity. The basic hardware layer consists of a dual simplex channel made up of a transmit and receive pair, collectively referred to as a link. The total bus speed of 2.5 Gb / s means that the bandwidth for each PCI Express lane is 250 Mb / s in each direction. Taking into account the loss of protocol overhead, about 200 Mb / s is available for each device. This bandwidth is 2-4 times higher than what was available for PCI devices. And, unlike PCI, if the bandwidth is distributed among all devices, then it goes to each device in full.

Today there are several versions of the PCI Express standard, differing in their bandwidth.

PCI Express x16 bus bandwidth for different PCI-E versions, Gb / s:

• 32/64
• 64/128
• 128/256

PCI-E bus formats

At the moment, there are various options for PCI Express formats, depending on the purpose of the platform - a desktop computer, laptop or server. Servers that require more bandwidth have more PCI-E slots, and these slots have more trunks. In contrast, laptops can only have one line for mid-speed devices.

PCI Express x16 graphics card.

PCI Express expansion cards are very similar to PCI cards, but PCI-E slots have increased adhesion to ensure that the card does not slip out of the slot due to vibration or during shipping. There are several form factors of PCI Express slots, the size of which depends on the number of lanes in use. For example, a bus with 16 lanes is designated PCI Express x16. Although the total number of lanes can be as high as 32, in practice most motherboards are now equipped with PCI Express x16.

Smaller form factors can be plugged into larger slots without compromising performance. For example, a PCI Express x1 card can be plugged into a PCI Express x16 slot. As with the PCI bus, you can use a PCI Express extension cable to connect devices if necessary.

The appearance of various types of connectors on the motherboard. From top to bottom: PCI-X slot, PCI Express x8 slot, PCI slot, PCI Express x16 slot.

Express Card

The Express Card standard offers a very simple way to add hardware to a system. The target market for Express Card modules is laptops and small PCs. Unlike traditional desktop expansion cards, the Express card can plug into the system anytime the computer is running.

One of the popular Express Cards is the PCI Express Mini Card, designed as a replacement for Mini PCI cards. A card created in this format supports both PCI Express and USB 2.0. The dimensions of the PCI Express Mini Card are 30 × 56 mm. PCI Express Mini Card can connect to PCI Express x1.

Benefits of PCI-E

PCI Express technology has provided an advantage over PCI in the following five areas:

1. Higher productivity. With just one lane, PCI Express has twice the bandwidth of PCI. In this case, the throughput increases in proportion to the number of lines in the bus, the maximum number of which can reach 32. An additional advantage is that information on the bus can be transmitted simultaneously in both directions.
2. Simplification of I / O. PCI Express takes advantage of buses such as AGP and PCI-X while offering less complex architecture and comparative ease of implementation.
3. Layered architecture. PCI Express offers an architecture that can accommodate new technologies and does not require significant software upgrades.
4. Next generation I / O technologies. PCI Express provides new opportunities for data acquisition using concurrent data transfer technology, ensuring timely information receipt.
5. Ease of use. PCI-E makes it much easier for the user to upgrade and expand the system. Additional Express card formats, such as ExpressCard, dramatically increase the ability to add high-speed peripherals to servers and laptops.

Conclusion

PCI Express is a peripheral bus technology that replaces technologies such as ISA, AGP and PCI. Its use significantly increases the performance of the computer, as well as the user's ability to expand and update the system.

Briefly about history ...

For the first time, a separate interface designed to becomea replacement for the PCI bus for video cards, was introduced in 1997. AGP (Accelerated Graphics Port) - this is how Intel presented its new development simultaneously with the official announcement of the chipset for Intel Pentium II processors.

Declared benefitsAGP before its predecessorPCIwere significant:

• higher operating frequency (66 MHz);
• increased bandwidth between the video card and the system bus;
• direct transfer of information between the video card and RAM, bypassing the processor;
• improved power supply system;
• high-speed access to shared memory.

Due development standardAGP 1x (AGP 1.0 specification) was not received due to the low speed of working with memory and was almost immediately improved, and its speed was doubled - this is how the AGP 2x interface appeared. Transmitting 32 bits (4 bytes) per cycle, the AGP 2x port could deliver a peak performance unprecedented at that time of 66.6x4x2 = 533 MB/ s.

In 1998, the AGP 4x standard (AGP 2.0 specification) was released, which provides the transfer of up to 4 blocks of information per cycle. At the same time, the signal voltage of the port was reduced from 3.3 to 1.5 V. The maximum throughput of AGP 4x became about 1GB/ s... In the future, the development of specifications was protracted - the reason for this was the very low speed of the existing video accelerator fleet at that time, as well as the low speed of exchange with RAM.

As soon as the technical progress "rested" on the bus, which turned out to be too small for the transmission of huge data streams by modern video cards, a new standard was approved - AGP 8x (AGP 3.0 specification). As you might have guessed, it can transmit up to 8 blocks of information per clock cycle and has a peak bandwidth of 2GB/ s... The AGP 8x bus is backward compatible with AGP 4x.

The high-tech industry is always skyrocketing. The volumes of transmitted and transmitted data are increasing, textures and their quality are growing, all this certainly forces each of the manufacturers to shake things up for themselves and produce something new and high-tech (standard, specifications, protocol, interface) that will bind a new round in the spherehi- tech.

Officially, the first basic PCI Express specification appeared in July 2002, thus marking the day of the gradual "death" of AGP 8x ...

Introduction

At the moment, the modern Intel P45 / X48 chipset has official support for PCI Express 2.0 specifications, which the very common Intel P35 could not boast of. For those who are just going to buy a modern motherboard on the Intel platform, the choice remains quite obvious - the P45 / X48 chipset, and you will not face the dilemma of "enough or not enough" PCI Express 1.1 for the current hi-end or middle-end video card. But what about the owners of the P35s? Should I run to the store again?

In our today's material, we will try to dot the "I" regarding the advantages of PCI-E 2.0 over PCI-E 1.1 for modern accelerators. We will also experimentally analyze the performance of video cards when working with various interfaces, on the basis of which a conclusion will be drawn about the practical value of PCI-E 2.0.

And before proceeding with any objective tests, let's delve a little deeper into the theory, namely, we will figure out how it all works in general.

PCI- Express- briefly about the main

As mentioned above, the basic PCI Express specification appeared in July 2002. With its high speed and peak performance, PCI Express leaves no room for its predecessor AGP. In terms of its software model, the new PCI-E interface is in many respects similar to PCI, which makes it easy to adapt the current fleet of all kinds of devices to the new interface without significant software "adjustments".

The principle of operation of PCI Express is based on serial data transmission. The bus is a star topology packet network. PCI-E devices communicate using a bi-directional point-to-point connection called "Line". Each PCI Express connection can consist of one (1x) or multiple lanes (4x, 16x, etc.).

For a basic PCI-Express 1x configuration, the theoretical bandwidth is 250 MB / s in each direction (transmit / receive). Accordingly, for PCI-E x16, this value is 250 MB / s x 16 = 4 GB / s.

It is noteworthy that from the physical side, the interface allows, for example, any motherboard with a PCI-E 1x interface to work confidently not only in the standard one, but also in any other PCI Express slot of higher bandwidth (4x, 16x, etc.). In this case, the maximum number of involved lines depends only on the properties of the device.

In all high-speed protocols, the issue of noise immunity always arises. In this regard, PCI Express uses the well-known scheme of 8/10 or excess traffic (8 bits of data transmitted over the channel are replaced by 10 bits, thus additional information is generated, about 20% of the total "flow").

PCIExpress 2.0

The standard was officially approved on January 15, 2007. In the second revision of PCI Express, the throughput of one channel has significantly increased - up to 5 Gb / s (PCI Express 1.x - 2.5 Gb / s). This means that now for the x16 line the maximum data transfer rate can reach 8 GB / s in both directions versus 4 GB / s for the old PCI Express 1.x.

Notably, PCI Express 2.0 is fully compatible with PCI Express 1.1. In fact, this means that old video cards will work quietly in motherboards with new connectors, and new video adapters will work without problems in old PCI Express 1.x slots.

Perhaps, with this theory and the main features of PCI Express, let's round off, it's time to start the corresponding tests, which we, in fact, will do, however, a little below, but for now, let's get to know the test participants in detail.

About test participants

Unfortunately, it was not possible to cover a larger set of graphics accelerators at the time of testing, which we will definitely fix in the future. Low-End video cards were deliberately excluded from the tests, since they are of little use for high-resolution modes (over 1280x1024) with maximum picture detail, where the advantages of PCI-E 2.0 over the junior PCI-E 1.1 can be revealed.

Almost all modern motherboards are currently equipped with a PCI-E x16 expansion slot. This is not surprising: a discrete graphics accelerator is installed in it, without which the creation of a productive personal computer is generally impossible. It is about its prehistory of appearance, technical specifications and possible modes of operation that will be discussed in the future.

Prehistory of the appearance of the expansion slot

In the early 2000s, with the AGP expansion slot, which at that time was used for installation, a situation developed when the maximum performance level was reached and its capabilities were no longer enough. As a result, the PCI-SIG consortium was created, which began to develop the software and hardware components of the future slot for installing graphics accelerators. The fruit of his creativity was the first PCI Express 16x 1.0 specification in 2002.

To ensure compatibility of the two discrete graphics adapter ports that existed at that time, some companies developed special devices that allowed installing outdated graphics solutions in a new expansion slot. In the language of professionals, such a development had its own name - PCI-E x16 / AGP adapter. Its main purpose is to minimize the cost of upgrading a PC by using components from the previous configuration of the system unit. But this practice did not become widespread for the reason that entry-level video cards on the new interface had a cost almost equal to the price of an adapter.

In parallel with this, simpler modifications of this expansion slot for external controllers were created, which replaced the usual PCI ports at that time. Despite the external similarity, these devices were significantly different. If AGP and PCI could boast of parallel information transfer, then PCI Express was a serial interface. Its higher performance was ensured by a significantly increased data transfer rate in duplex mode (information in this case could be transmitted in two directions at once).

Transfer rate and encryption method

In the designation of the PCI-E x16 interface, the number indicates the number of used bands for data transfer. In this case, there are 16. Each of them, in turn, consists of 2 pairs of wires for transmitting information. As noted, the higher speed is provided by the fact that these pairs are operating in full duplex mode. That is, the transfer of information can go in two directions at once.

To protect against possible loss or distortion of the transmitted data, a special information protection system called 8V / 10V is used in this interface. This designation is deciphered as follows: for correct and correct transmission of 8 data bits, it is necessary to supplement them with 2 service bits to perform a correctness check. In this case, the system is forced to transmit 20 percent of the service information, which does not carry a payload for the computer user. But this is a payment for the reliable and stable operation of the graphic subsystem of a personal computer, and you certainly cannot do without it.

PCI-E versions

The PCI-E x16 slot looks the same on all motherboards. Only here the speed of information transfer in each case may differ significantly. As a result, the speed of the device is also different. And the modifications of this graphical interface are as follows:

• 1st modification PCI - Express x16 v. 1.0 had a theoretical bandwidth of 8 GB / s.
• 2nd generation PCI - Express x16 v. 2.0 already boasted a doubled bandwidth - 16 GB / s.
• A similar trend has continued for the third version of this interface. In this case, this figure was set at around 64 GB / s.

It is impossible to visually distinguish by the location of the contacts. Moreover, they are compatible with each other. For example, if a graphics adapter card is installed in the 3.0 slot, which corresponds at the physical level to specifications 2.0, then the entire processing system will automatically switch to the lowest speed mode (that is, 2.0) and will function in the future with a bandwidth of 64 Gb / s. ...

First generation PCI Express

As noted earlier, PCI Express was first introduced in 2002. Its release marked the emergence of personal computers with several graphics adapters, which, moreover, could boast even one accelerator installed with increased performance. AGP 8X standard allowed to get a bandwidth of 2.1 Gb / s, and the first revision of PCI Express - 8 Gb / s.

Of course, there is no need to talk about an eight-fold increase. 20 percent of the increase was used for the transmission of service information, which made it possible to find errors.

Second modification PCI-E

The first generation of this one was replaced in 2007 by PCI-E 2.0 x16. Video cards of the 2nd generation, as noted earlier, were physically and programmatically compatible with the first modification of this interface. Only in this case the performance of the graphics system was significantly reduced to the level of the PCI Express 1.0 16x interface version.

Theoretically, the information transfer limit in this case was 16 Gb / s. But 20 percent of the gain received was spent on service information. As a result, in the first case, the real transfer was: 8 Gb / s - (8 Gb / s x 20%: 100%) = 6.4 Gb / s. And for the second version of the graphical interface, this value was already like this: 16 Gb / s - (16 Gb / s x 20%: 100%) = 12.8 Gb / s. Dividing 12.8 Gb / s by 6.4 Gb / s, we get a real practical increase in performance by 2 times between the 1st and 2nd PCI Express executions.

Third generation

The last and most relevant update to this interface was released in 2010. The peak PCI-E x16 speed in this case increased to 64 Gb / s, and the maximum power of the graphics adapter without additional power supply in this case can be equal to 75 W.

Configuration options with multiple graphics accelerators in one PC. Their pros and cons

One of the most important innovations of this interface is the ability to have multiple graphics adapters in x16 at once. In this case, video cards are combined with each other and form, in essence, a single device. Their overall performance is summed up, and this allows you to significantly increase the speed of the PC from the standpoint of processing the displayed image. For solutions from NVidia, this mode is called SLI, and for graphics processors from AMD - CrossFire.

The future of this standard

The PCI-E x16 slot will certainly not change for the foreseeable future. This will allow more productive video cards to be used as part of outdated PCs and, due to this, to carry out a phased upgrade of the computer system. Now the specifications of the 4th version of this data transfer method are being worked out. For graphics adapters, in this case, a maximum of 128 Gb / s will be provided. This will allow you to display the image on the monitor screen as "4K" or more.

Outcomes

Be that as it may, and PCI-E x16 is currently the uncontested graphics slot and interface. It will be relevant for a long time to come. Its parameters allow you to create both entry-level computer systems and high-performance PCs with multiple accelerators. It is due to this flexibility that no significant changes are expected in this niche.

WiFi modules and other similar devices. The development of this bus was started by Intel in 2002. The PCI Special Interest Group, a non-profit organization, is currently developing new versions of this bus.

At the moment, the PCI Express bus has completely replaced such outdated buses as AGP, PCI and PCI-X. The PCI Express bus is located at the bottom of the motherboard in a horizontal position.

PCI Express is a bus that has been designed around the PCI bus. The main differences between PCI Express and PCI lie at the physical level. While PCI uses a common bus, PCI Express uses a star topology. Each device is connected to a common switch with a separate connection.

The PCI Express software model follows the PCI model in many ways. Therefore, most of the existing PCI controllers can be easily modified to use the PCI Express bus.

PCI Express and PCI slots on the motherboard

In addition, the PCI Express bus supports such new features as:

• Hot plugging devices;
• Guaranteed speed of data exchange;
• Energy consumption management;
• Integrity control of transmitted information;

How the PCI Express bus works

The PCI Express bus uses a bi-directional serial connection to connect devices. Moreover, such a connection can have one (x1) or several (x2, x4, x8, x12, x16 and x32) separate lines. The more such lines are used, the higher the data transfer rate can be provided by the PCI Express bus. Depending on the number of lanes supported, the sizing on the motherboard will differ. There are slots with one (x1), four (x4) and sixteen (x16) lines.

Visual demonstration of PCI Express slot sizes

Moreover, any PCI Express device can work in any slot if the slot has the same or more lines. This allows you to install a PCI Express card with an x1 slot in an x16 slot on your motherboard.

PCI Express bandwidth depends on the number of lanes and the bus version.

Examples of PCI Express devices

PCI Express is primarily used to connect discrete video cards. Since the appearance of this bus, absolutely all video cards have been using it.

GIGABYTE GeForce GTX 770 Graphics Card

However, this is not all that the PCI Express bus can do. It is used by manufacturers of other components.

SUS Xonar DX sound card

SSD OCZ Z-Drive R4 Enterprise

Alexey Borzenko,
Ph.D., associate professor of RRTA

The PCI Express interface (formerly known as 3GIO) is based on open standards and acts as the successor to PCI and its variants for server and client I / O systems. Unlike PCI and PCI-X, which are based on a 32- and 64-bit parallel bus, PCI Express uses high-speed serial communication technology similar to that used in Gigabit Ethernet, Serial ATA (SATA), and Serial Attached SCSI (SAS) ... PCI Express reflects the general trend in the computer industry to replace legacy parallel common buses with high-speed, point-to-point serial connections.

The new bus technology provides transfer rates that will be sufficient given the evolution of processors and I / O subsystems for at least the next 10 years.

Compared to PCI, PCI Express technology has the following advantages:

• high throughput - in the first version, the theoretical peak throughput will be 5-80 Gbps, depending on the implementation;
• daisy chain for performance scalability;
• separate point-to-point connection for each device instead of a common PCI bus;
• low latency for server architecture;
• Smaller connector sizes and simplified system design
• advanced functions.

Over the next decade, PCI Express will gradually replace the parallel PCI, PCI-X, and AGP buses. It will first supplant tires that require additional performance and features. For example, PCI Express will initially replace the AGP 8X graphics bus in client systems, providing high bandwidth and multimedia traffic support. It will coexist with the PCI-X bus and gradually replace it in server systems.

PCI bus

The PCI bus, introduced in 1992, has become the backbone of the I / O system for almost all computer platforms. The original 33-MHz, 32-bit implementation provided a theoretical peak performance of 133 MB / s. In subsequent years, the architecture of the platform evolved, various functions were shifted to PCI variants with higher bandwidth (Table 1), including AGP and PCI-X.

Table 1. Bandwidth of PCI, PCI-X and AGP buses

If you take a closer look at the signaling technology used in PCI, it becomes clear that it is no longer possible to increase the performance of this multidrop parallel bus. The point is that it is difficult for the PCI bus to implement an increase in frequency or a decrease in voltage. In addition, it does not support features such as advanced power management, peripheral replacement and hot plugging, and quality of service (QoS) features for guaranteed bandwidth for real-time operations. Finally, all available PCI bandwidth does not support simultaneous data transfer in both directions. Many data networks provide concurrent traffic, which minimizes message latency.

Client systems

The first PCI bus was designed to support 2D graphics, high-performance hard drives, and LANs. Soon after the advent of PCI, increased 3D graphics bandwidth requirements exceeded the 32-bit 33 MHz PCI bus. To address this issue, Intel Corporation (http://www.intel.com) worked with several graphics card manufacturers to develop the AGP specification for a dedicated high-speed graphics bus. The AGP bus freed the PCI system from transferring graphics, which allowed its bandwidth to be used for other data transfer and I / O operations. In addition, Intel subsequently added dedicated USB 2.0 and Serial ATA channels to its chipset southbridge (NMC), further reducing the PCI I / O load. In fig. 1 shows the internal architecture of a typical PC client system and the I / O and graphics bus bandwidth.

Client system bottlenecks

There are several client buses that can limit performance due to continuous improvements in CPU, memory, and I / O: the PCI bus, the AGP bus, and the northbridge link.

PCI Bus. The PCI bus provides transfer rates up to 133 MB / s for attached I / O devices. A number of I / O devices are capable of loading a significant portion of this bandwidth, so if multiple I / O devices are connected, the shared PCI bus will not be able to handle the traffic.

In fig. Figure 2 shows the bandwidth requirements of various network protocols, video applications, and external devices that the PCI bus serves. As you can see, the multipoint shared PCI bus has a hard time working with modern devices. The problem is exacerbated by the emergence of new peripherals that use even higher transfer rates.

For example, Gigabit Ethernet requires a bandwidth of 125 MB / s, in other words, this network protocol actually completely loads the PCI bus with 133 MB / s. IEEE 1394b has a maximum bandwidth of 100 MB / s, and it also fully utilizes the standard PCI bus.

AGP. In the past decade, video performance requirements have doubled every two years. During this period, the graphics bus has moved from PCI to AGP, then from AGP to AGP 2X, AGP 4X, and finally to today's AGP 8X.

AGP 8X runs at 2.134 GB / s. Despite this bandwidth, the progressive increase in AGP bus performance requirements poses significant design challenges and increases the cost of connections. As with the PCI bus, expanding the capabilities of the AGP bus becomes more difficult and expensive as frequencies increase.

Channel between the north and south bridges. PCI load also affects Northbridge and Southbridge communication, especially when using SATA drives and USB devices. In the future, this will require a channel with more bandwidth.

Server systems

In servers, the original 32-bit, 33 MHz PCI bus has been expanded to 64-bit 66 MHz with 532 MB / s bandwidth. The 64-bit bus frequency has been increased to 100 and to 133 MHz - this option is called PCI-X. This bus connects the NMC server system (or high-end dual-processor workstation) to the expansion slots, Gigabit Ethernet and Ultra320 SCSI controllers integrated on the motherboard. The 64-bit, 133 MHz PCI-X bus provides a peak bandwidth of 1 GB / s between the system HMC and the I / O device. This is now sufficient for most I / O, including Gigabit Ethernet, Ultra320 SCSI, and 2 Gbps Fiber Channel. However, PCI-X, like PCI, is a shared bus with inherent disadvantages.

The PCI Special Interest Group (PCI SIG, http://www.psisig.com) developed the PCI-X 2.0 specification, which describes a 64-bit, 266-MHz PCI-X bus with twice the transfer rate of 133- MHz PCI-X. However, there are major design issues with the extended PCI-X parallel bus. The connectors are bulky and expensive, and the stringent design requirements dramatically increase the cost of motherboards as frequencies increase. In addition, at high frequencies, only one I / O device can be connected to the PCI-X 2.0 bus in a point-to-point configuration.

Server system bottlenecks

In fig. 3 shows the internal system interconnects in a typical 2-processor server system. In this architecture, bandwidth expansion is provided through a proprietary interface between the Northbridge and PCI-X bridges. Multiple PCI-X buses connect to high-speed expansion slots, 10Gb Ethernet, and SAS / SATA drives. But this architecture has several disadvantages. Dedicated PCI-X bridge dies connect multiple parallel PCI-X buses to a dedicated HMC serial interconnect. This approach is costly, inefficient, and introduces transmission delays between the I / O devices and the northbridge. For example, this approach involves connecting a 10 Gbps serial fabric to a 64-bit parallel bus, which in turn connects through a proprietary PCI-X bridge die to the serial interconnect on the north bridge.

Rice. 3. Modern dual-processor processor architecture.

In addition, external I / O technology in next-generation servers requires much higher bandwidth than the 133 MHz PCI-X bus can provide. These technologies include fabrics such as 10Gb Ethernet, 10Gbps Fiber Channel and 4x Infiniband, as well as future high-speed hard drive interfaces SATA and 3Gbps SAS. In the case of a 10 Gbps fabric, each 10 Gbps port can transfer data in both directions at a peak speed of 2 Gb / s, and a 133-MHz PCI-X bus provides a maximum speed of 1 Gb / s in one direction to one moment of time. This means that the 133MHz PCI-X bus is capable of handling the peak bandwidth of such fabrics by no more than 50%.

While PCI-X 2.0 at 266 MHz will double the PCI-X peak bandwidth to 2GB / s, it still won't be enough for the total 4GB / s required by the dual-port 10Gb / s fabric controller. It is clear that client systems and servers need to replace the parallel PCI bus and its variants.

PCI Express

PCI Express provides a scalable, high-speed serial I / O bus. The PCI Express layered architecture supports existing PCI applications and drivers through backward compatibility with the existing PCI model. Specifically, the PCI Express architecture defines a high-performance, scalable point-to-point serial bus. A PCI Express link consists of two unidirectional links, each implemented as a transmit and receive pair for simultaneous transmission in both directions. Each pair consists of two low voltage differential signal pairs. A sync timer is built into each pair and uses an 8b / 10b sync coding scheme to achieve high baud rates. In fig. 4 shows PCI versus PCI Express lanes.

Rice. 4. PCI versus PCI Express.

Layered PCI Express Architecture Level Configuration / OS defines a standard mechanism (in accordance with the PCI Plug-and-Play specification) for device initialization, numbering and configuration. This layer communicates with the software layer that initiates data transfer between peripheral devices or receiving data from connected peripherals. PCI Express was designed to be compatible with existing operating systems, but future operating systems will be required to support the technology's powerful features. Level Software generates read and write requests to peripheral devices. PCI Express provides provisioning and PCI software compatibility. As with PCI, the PCI Express provisioning model allows the OS to discover new hardware devices and allocate system resources. PCI Express saves PCI configuration space and I / O programming, and all operating systems will boot without modification on PCI Express systems. The PCI software execution model is also preserved, which allows you to run existing software without any modification. Level Transactions reads and writes requests from the software layer to the data link layer using a packet-based protocol and ensures that the response packets correspond to the software requests. This layer supports 32-bit and extended 64-bit memory addressing, PCI memory, I / O and configuration address space, and a new message space for messages such as interrupts and resets. Duct the layer adds packet sequencing and cyclic redundancy code (CRC) error detection to data packets, creating a reliable mechanism for transferring data between the system HMS and the I / O controller. Physical the layer is based on PCI Express dual unidirectional links. This provides flexibility and allows for different technologies and frequencies. With this approach, the original silicon technology can be replaced over time with innovations that remain backward compatible. For example, fiber optic technology can be used to increase data transfer rates. Mechanical the level determines the form factors of the peripherals. PCI Express Architecture Layers

PCI Express bandwidth can be scaled by adding signal pairs to form multiple lanes between two devices. The specification supports x1, x4, x8 and x16 line widths and splits the data bytes across the lines accordingly. After the two agents at both ends of the PCI Express link agree on the bandwidth and transmission rate, the data bytes are transmitted split across the encoded lines.

The base channel x1 has a raw bandwidth of 2.5 Gbps. Since the bus operates in two directions (data can be transmitted simultaneously in both directions), the effective raw transfer rate is 5 Gbps. Table 2 shows the data transfer rates with and without coding when implementing the x1, x4, x8 and x16 lines, which are defined in the first version of PCI Express.

Table 2. PCI Express Bandwidth

In future PCI Express implementations, the bandwidth will be further increased. For example, after the appearance of the second generation PCI Express, the transmission frequency will increase at least twice. With a point-to-point architecture, the entire bandwidth of each PCI Express bus is allocated to the device at the end of the link. Multiple PCI devices can work simultaneously without interfering with each other.

PCI Express, unlike PCI, has minimal sideband signals, and timestamps and address information are embedded in the data. That is why this technology provides a high bandwidth per pin of an I / O connector compared to PCI (Figure 5). As a result, connectors are more efficient, compact and cheaper.

PCI Express technology reliably delivers higher data transfer rates through low voltage differential signals. With this approach, the signal goes from the source to the receiver along two lines: one sends a "positive" image, the other sends a "negative" or "inverted" image of the signal. Due to strict routing rules, noise affecting one line affects the other as well. The receiver receives both signals, inverts the negative version back to the positive one, and adds the two collected signals, as a result, noise is effectively removed.

The original PCI Express specification specified graphics cards up to 75W. A new PCI Express graphics specification is under development for cards up to 150W. These specifications meet the requirements of graphics adapters, which currently have a power limit of 41W for mainstream AGP cards and 110W for AGP Pro 110 cards.

Advanced PCI Express Features

PCI Express provides advanced features that will gradually be implemented as they are supported by the OS and devices, and as applications use them. These features include:

• advanced energy management;
• support for real-time data traffic;
• hot swap;
• data integrity and error handling.

Advanced energy management

Management in PCI Express can reduce power consumption when the bus is not active (that is, no data is sent between components and peripherals). The PCI Express interface must be active at all times for the transmitter and receiver to work in sync. To do this, if there is no data to transmit, empty characters are continuously sent, the receiver decodes them and discards them. This process consumes additional energy, which, in particular, reduces the battery life of laptops and PDAs.

To address this issue, the PCI Express specification defines two low power channel states and the Active-State Power Management (ASPM) protocol. When not in use, PCI Express can enter one of two low power states. These states save energy, but require a recovery time to resynchronize the transmitter and receiver when data needs to be transmitted. The longer the recovery time (or lag), the lower the power consumption.

Real-time traffic support

PCI Express, unlike PCI, supports isochronous (or time-dependent) data transfer and different QoS levels. These functions are implemented using "virtual circuits", which ensure that specific data packets arrive at their final address at a specific point in time. PCI Express supports multiple isochronous virtual circuits (each with an independent session) per lane. All of these channels may have different availability. This complete solution is designed for applications that require real-time data delivery (such as, for example, working with audio and video in real time).

Hot swap

PCI-based systems do not have built-in support for hot swapping I / O cards. Already after the release of the PCI standard, a function of hot swapping of server cards and PC Cards with limited capabilities was developed as an addition to it. These solutions are designed to meet the growing demands of servers and laptops. First, it is often difficult or impossible to schedule a server shutdown to replace or install peripheral cards. Hot-swappable I / O devices minimize downtime. Second, laptop users need to hot-swap cards that provide I / O functionality such as mobile disk and networking.

PCI Express has original support for hot swapping I / O peripherals. A single programming model can be used for all PCI Express form factors.

Data Integrity and Error Handling

PCI Express maintains link-level data integrity for all types of transaction packets and data links. This ensures data integrity in transit for high availability applications, especially those running on server systems. PCI Express also supports PCI error handling and uses an improved error reporting and handling mechanism to expand the capabilities of fault isolation and recovery solutions.

PCI Express Form Factors

Various PCI Express form factors have been designed for client systems, servers, and laptop computers. These include standard and low-profile cards for desktops, workstations and servers, Mini Card for laptops, ExpressCard for laptops and desktops, and Server I / O Modules (SIOM).

Standard and low profile cards

Today's standard and low-profile PCI cards are used on a variety of platforms, including servers, workstations, and desktops. PCI Express also defines standard and low-profile cards that can replace and coexist with legacy PCI cards. These cards are the same dimensions as PCI cards and have rear brackets for external cable connections.

PCI and PCI Express cards differ in I / O connectors - the x1 PCI Express slot has 36 pins, while the standard PCI connector has 120 pins.

The x1 PCI Express connector is much smaller than the PCI Card. There is a small knockout next to the PCI Express slot that prevents you from inserting it into a PCI slot. Standard and low-profile form factors also support x4, x8, and x16 implementations. In fig. Figure 6 shows the dimensions of the PCI connectors compared to the PCI, AGP 8X, and PCI-X connectors they will replace on the motherboard.

Table 3 lists the compatibility requirements for standard and low-profile PCI Express cards. The x1 card can be used in all four motherboard slots: x1, x4, x8, and x16. When an x1 card is inserted into a slot with a higher speed, the link layer reduces the link speed to x1.

Table 3. PCI Express Card Compatibility

Migrating to PCI Express Cards

Client system cards will gradually migrate from PCI connectors to x1 PCI Express connectors. Workstations will accordingly move from PCI to x1 PCI Express slots and from PCI-X to x4 PCI Express slots. The AGP 8X connector will be replaced with an x16 PCI Express connector. Unlike AGP, it can be used for other PCI Express cards if no PCI Express graphics card is required.

Servers will gradually move away from PCI-X connectors to mainly x4 and x8. Using a combination of PCI Express and PCI / PCI-X slots in server systems will allow customers to adapt to the new technology while maintaining legacy support.

Let's look at an example of a typical modern client system and PCI Express riser card. The PCI system board contains five standard PCI slots and one AGP slot. The PCI Express motherboard also has six I / O slots, but only three of them are PCI slots, and two more are x1 PCI Express connectors and one is an x16 PCI Express slot replacing the AGP 8X slot. The PCI Express connectors on the motherboard are sometimes blackened to distinguish them from the white PCI slots and brown AGP slots.

Of course, the first devices to switch to PCI Express cards will be cards with higher bandwidth requirements. On client systems, these are graphics, IEEE 1394, Gigabit Ethernet and TV tuners, and on server systems, Ultra320 SCSI RAID cards, Fiber Channel HBAs, and Gigabit Ethernet and 10 Gigabit Ethernet cards. It is expected that the cost of these boards will be comparable to the price of similar PCI-X, and in some cases even less. Other cards will also gradually migrate to PCI Express, but it may take several years before low-cost, low-bandwidth cards (like modems) start using this technology. Thus, as was the case with the transition from ISA to PCI bus, PCI and PCI Express will coexist for many years to come.

PCI Express Mini Card

PCI Express Mini Cards will replace Mini PCIs, which are small internal cards similar in functionality to desktop PCI cards. Mini PCI cards are used primarily for networking functions in mass-produced or custom-made notebook computers. The size of a PCI Express Mini Card is half the size of a Mini PCI, which allows laptop designers to provide room for one or two cards depending on the size of the computer.

PCI Express Mini Card can use PCI Express and / or USB 2.0. The PCI Express Mini Card slot on the motherboard must support both x1 PCI Express lane and USB 2.0. USB 2.0 support will ease the transition to PCI Express because it takes time for peripheral manufacturers to implement PCI Express support in their chipsets. During the transition period, PCI Express Mini Card can be easily connected using USB 2.0.

ExpressCard

The ExpressCard is a small modular add-on card that should replace the PC Card over the next few years. The ExpressCard specification was developed by the Personal Computer Memory Card International Association (PCMCIA, http://www.pcmcia.org). The ExpressCard form factor provides a smaller, cost-effective PC Card replacement for better performance. Like PCI Express Mini Card, ExpressCard module supports x1 PCI Express and USB 2.0 lanes. Its low cost makes it ideal for smaller form factor desktops. The ExpressCard module is also low power and hot pluggable. Most likely, ExpressCard will be used in network cards, hard drives and future I / O technologies.

PCI Express Server I / O Module

The massive appearance of SIOM modules is expected after the release of the second generation PCI Express. PCI Express SIOM provides a form factor that is easy to install and replace. It will be modular, which will allow you to install and maintain I / O cards without interrupting the system and without opening the computer case.

SIOM provides for a more radical form factor change than other PCI Express options. It will solve many problems with PCI and PCI-X server cards. SIOM design makes cards more reliable, which is especially important in data centers. The module was also designed with forced ventilation in mind, since powerful servers tend to generate high heat. Cooling air can flow from the back, top or bottom of the module. This flexibility gives system designers more freedom to evaluate cooling options for SIOM-equipped rack systems.

SIOMs in the largest form factor are capable of relatively complex functions and utilize the full range of PCI Express lanes.

Examples of PCI Express Systems

Let's consider how PCI Express technology can be implemented in client and server systems. Initially, the x16 PCI Express link will replace the AGP bus between the graphics subsystem and the northbridge. The PCI Express option can also replace the channel between both NMC bridges. There are also several PCI Express lanes from the south bridge to the network interface controller (NIC), IEEE 1394 devices, and other peripherals. The Southbridge will continue to support legacy PCI slots.

This architecture provides customers with several important benefits. Desktop systems will be equipped with both PCI and PCI Express buses for a long time. First generation PCI Express servers will also have PCI-X slots for legacy PCI-X cards. To simplify the transition, protection is provided against erroneous insertion of PCI into PCI Express slots and PCI Express cards into PCI slots. In addition, PCI Express enables widespread use of Gigabit Ethernet, 10 Gigabit Ethernet, 1394b, and other high-speed devices in client systems. It also supports the growing demands on graphics bandwidth.

PCI Express can be used in a dual-processor server architecture, greatly simplifying the system. PCI Express channels for I / O devices and slots connect directly to the northbridge. There are several advantages to this approach. The first is high bandwidth for next generation I / O like 10 Gigabit Ethernet and x4 Infiniband fabrics. For example, an x8 PCI Express lane is capable of providing the peak bandwidth required by a dual-port 10 Gbps controller.

Secondly, implementation costs become less. More slots and onboard I / O can be connected to the system chipset, which reduces the number of bridge chips and reduces signal routing requirements on the system board. Finally, by eliminating the use of the PCI-X bridge chip, the transfer lag between I / O devices and the CPU and memory is reduced.

Thus, PCI Express technology provides a reliable and scalable serial connection that is backward compatible with PCI. Like PCI, it will be used on a wide variety of existing platforms, including servers, laptops, desktops and workstations. It will also allow for innovative design of modular computer systems.