PCB design guidelines (mini-FAQ on PCB layout). PCB layout and EMC for MB90 series microcontrollers

Definitions:

Electromagnetic compatibility, EMC (Electromagnetic compatibility, EMC): the ability during operation not to make an excessive contribution to the environment by electromagnetic radiation. When this condition is met, all electronic components work together correctly.

Electromagnetic interference, EMI (Electromagnetic interference, EMI): Electromagnetic energy emitted by one device that can cause performance degradation in another device.

Electromagnetic immunity, EMPU (Electromagnetic immunity, or susceptibility, EMS): tolerance (resistance) to the effects of electromagnetic energy.

EMC design: 4 main rules

Rules problem: The more rules you have, the harder it is to follow them all. The prioritization of their implementation is different.

Let's say that when creating a multilayer printed circuit board, you need to route a high-frequency signal from an analog component to a digital one. Naturally, you want to minimize the chance of an electromagnetic compatibility (EMC) problem. Doing a search on the Internet, you find three recommendations that seem to be relevant to your situation:

1. Minimize High Frequency Bus Lengths
2. Separate power and ground rails between analog and digital parts of the circuit
3. Do not break ground polygons with high-frequency conductors

Your vision of the three possible wiring options is shown in Figure 1.

In the first case, the traces are routed directly between the two components, and the land polygon remains solid. In the second case, a gap is formed in the polygon, and the traces pass across this gap. In the third case, the traces are laid along the gap in the polygon.

In each of these three cases, one of the above rules is violated. Are these alternative cases equally good because they satisfy two of the three rules? Are they all bad because each of them breaks at least one rule?

These are the questions PCB designers face every day. Choosing the right or wrong wiring strategy can result in the board either meeting all EMC requirements or having issues with external signals. In this case, the choice should be clear, but we will return to this later.

Problems are reduced by prioritizing recommendations. Design recommendations are useful if they are well understood and if they form part of a complete strategy. Once designers learn to prioritize recommendations and understand how those recommendations should be used, they can design good PCBs.

The following are the four main EMC rules based on the general characteristics of electronic products. In many cases, PCB designers deliberately break one of these rules in an attempt to fulfill more important ones.

Rule 1: Minimize the Signal Current Path

This simple rule appears in almost every list of EMC recommendations, but it is often either ignored or downplayed in favor of other recommendations.

Often the PCB designer doesn't even think about where signal currents flow and prefers to think of signals in terms of voltage instead of thinking in terms of current.

There are two axioms that every PCB designer should know:

- signal currents always return to their source, i.e. the current path is a loop
- signal currents always use the path with the lowest impedance

At frequencies of several megahertz and above, the signal current path is relatively easy to determine because the path with the lowest impedance is, in general, the path with the lowest inductance. On fig. 2 shows two components on a printed circuit board. The 50 MHz signal propagates along the conductor over the polygon from component A to component B.



We know that a signal of the same magnitude must propagate back from component B to component A. Suppose that this current (let's call it return) flows from component B's terminal, labeled GND, to component A's terminal, also labeled GND.

Since the continuity of the polygon is ensured, and the pins marked as GND, of both components are located close to each other, this leads to the conclusion that the current will take the shortest path between them (path 1). However, this is not correct. High frequency currents take the path of least inductance (or the path with the smallest loop area, the path of least turn). Most of the signal return current flows through the polygon in a narrow path directly below the signal trace (path 2).

If a polygon was made for any reason with a notch, as shown in Figure 3, then notch 1 will have little effect on signal integrity and emission. The other notch 2 can lead to significant problems; it conflicts with recommendation 2. The loop area increases significantly; the reverse currents are so intense that they flow along the discontinuity boundary.



At low frequencies (generally, kHz and below), the path of least impedance tends to be the path with the lowest signal frequency. For a printed circuit board with solid return current polygons, the resistance of the polygons tends to dissipate the current so that the current flowing between two distant points can propagate over a larger area of ​​the board, as shown in Figure 4.



On a mixed signal board with low frequency analog and digital components, this can be a problem. Figure 5 illustrates how a well-placed discontinuity in a ground plane can remedy the situation by capturing the low frequency return currents flowing through the ground in a designated area.



Rule 2: Don't Explode the Return Signal Polygon

This is right. We have just shown you an excellent example in a situation where making a break in the return signal current path was the right decision. However, as typical EMC engineers, we advise you never to do this. Why? Because a lot of the developments we've come across from well-understood people have been the result of inadvertently breaking Rule 1 and creating gaps in the return polygons. Moreover, often the gap was ineffective and unnecessary.

One suggestion is that the analog signal return current should always be isolated from the digital signal return current. This idea arose when analog and digital circuits operated at kilohertz frequencies. For example, boards used for digital audio often had noise problems due to the effect of low frequency digital signal currents propagating under the area of ​​the board where the sensitive analog amplifiers were located. Some time ago, audio designers tried to avoid this problem by separating the return current polygons to control the return paths and removing the analog current circuits from the digital ones.

Our students are challenged to solve a design challenge that requires protecting sensitive analog components (usually audio amplifiers or phase-locked oscillators) from the digital portion of the circuit by separating the signal return current path in such a way that low-frequency currents are isolated and high-frequency currents do not form interference. It's usually not obvious how this can be done, and quite often gaps in polygons create more problems than they solve.

A similar situation arises when wiring tires for automotive or aviation radio-electronic equipment. In such equipment, the return currents of the digital circuitry are often isolated from the common housing in order to protect the digital circuitry from being damaged by the high LF currents that can flow through the metal structure of the vehicle. EMI filtering and transient protection typically require connections to the chassis while the signal must be transmitted relative to the digital return signal bus.

When the package circuit and digital return current polygons share the same bus, they appear as a single discontinuous polygon. This sometimes creates confusion as to which ground an individual component should be connected to. In this situation, it's usually a good idea to wire the chassis bus and digital return on separate busses. The digital return polygon must be solid and cover the area under all digital components, traces, and connectors. The connection to the chassis must be limited to the area of ​​the board near the connectors.

Undoubtedly, there are situations where a well-placed break in the return current path is required. However, the most reliable method is one solid polygon for all return signal currents. In cases where a single low-frequency signal is susceptible to interference (able to mix with other signals on the board), tracing on a separate layer is used to return this current to the source. In general, never split or cut in a signal return current polygon. If you are still convinced that a cutout in the polygon is necessary to solve the problem of low-frequency isolation, consult an expert. Do not rely on design guidelines or applications and try to implement a circuit that has worked for someone else in a similar design.

Now that we are familiar with the two main EMC rules, we are ready to revisit the problem in Fig. 1. Which of the alternatives is the best? The first is the only one that does not violate the rules. If for some reason (outside of the design desire), a gap in the earthen polygon was required, then the third wiring option is more acceptable. Tracing along the discontinuity minimizes the area of ​​the signal current loop.

Rule 3: Don't Place High-Speed ​​Circuits Between Connectors

This is one of the most common board designs we have reviewed and evaluated in our lab. In simple boards, which were supposed to have no failures under all EMC requirements without any additional cost or effort, good shielding and filtering were nullified because this simple rule was violated.

Why is connector placement so important? Below a few hundred megahertz, the wavelength is on the order of a meter or more. The conductors on the board—possible antennas—have relatively short electrical lengths and therefore perform inefficiently. However, cables or other devices connected to the board can be quite effective antennas.

Signal currents flowing through conductors and returning through solid polygons create small voltage drops between any two points in the polygon. These voltages are proportional to the current flowing through the polygon. When all connectors are placed on the same edge of the board, the voltage drop is negligible.

However, high-speed circuit elements placed between connectors can easily create a potential difference between connectors of up to several millivolts or more. These voltages can induce excitation currents into the connected cables, increasing their radiation.

A board that meets all specifications when the connectors are at one end can be a nightmare for an EMC engineer if even one cabled connector is located at the opposite side of the board. Products that exhibit this type of problem (cables carrying voltages induced through a solid ground) are especially difficult to fix. Often this requires a fairly good screening. In many cases, this shielding would not be needed at all if the connectors were located on one side or in a corner of the board.

Rule 4. Control Signal Transition Time

A board running at 100 MHz should never meet the requirements for running at 2 GHz. A well-formed digital signal will have a lot of power in the lower harmonics and not as much power in the higher ones. By controlling the transition time of the signal, it is possible to control the power of the signal at higher harmonics, which is preferable for EMC. Excessively long transition times can lead to signal integrity and thermal problems. In the development and design process, a compromise must be reached between these competing prerequisites. A transition time of approximately 20% of the signal period results in an acceptable waveform, reducing problems due to crosstalk and radiation. Depending on the application, the transition time may be more or less than 20% of the signal period; however, this time should not be uncontrollable.

There are three main ways to change the edges of digital signals:
- the use of digital microcircuits of a series whose speed matches the required speed,
- placing a resistor or inductor on the ferrite in series with the output signal, and
- placing a capacitor in parallel with the output signal

The first way is often the simplest and most effective. Using a resistor or ferrite gives the designer more control over the transient and has less effect on changes that occur in logic families over time. The advantage of using a capacitor for control is that it can be easily removed when not needed. However, it must be remembered that capacitors increase the current of the RF source.

Note that trying to filter a single wire signal in the return current path is always a bad idea. For example, never route a low frequency trace through a gap in the return polygon in an attempt to filter out high frequency noise. After considering the first two rules, this should be obvious. However, boards using this incorrect strategy are sometimes found in our lab.

Generally speaking, in the process of designing the structure and layout of the board, it is necessary to prioritize to comply with EMC rules. These rules should not be compromised when trying to follow other EMC recommendations. However, there are a few additional recommendations that deserve attention. For example, it is important to provide adequate separation of the power rail, keep the I/O wires short, and provide for filtering of the output signals.

It is also a good idea to carefully select active devices. Not all pin-compatible semiconductor components are equivalent in terms of noise. Two devices with the same specification, but made by different manufacturers, can differ significantly in the noise they produce on the input, output, and power pins. This is especially true for highly integrated circuits such as microprocessors and large application specific integrated circuits (ASICs). It's a good idea to evaluate components from different vendors whenever possible.

And finally, revisit your design. Even if you are an experienced PCB designer and EMC expert, it is good to have someone who is knowledgeable about EMC analysis and familiar with PCB design. Have him critically review your design.

Whose advice can you trust? Trust anyone whose advice clearly helps you to fulfill the four main rules. A little extra attention during design can save a lot of time, money, and effort that would be wasted trying to get an uncompromising product to work right.

Translation of the article:
Dr. Todd Hubing, Dr. Tom Van Doren
Designing for EMC: The TOP 4 GUIDELINES
Printed Circuit Design & Manufacture, June 2003

Dr. Todd Huebing, Emeritus Professor of Electrical and Computer Engineering, twice awarded the prize "Best Symposium Publications" of the International Symposium of the Institute of Electrical and Electronics Engineers.

Dr. Tom Van Doren, professor of electrical and computer engineering at the Electromagnetic Compatibility Laboratory of the University of Missouri Roll.

Profit margins in consumer electronics are low, and manufacturers try to keep product costs low to stay competitive. For this reason, they require designers to use low-cost printed circuit boards (PCBs) and components while maintaining the desired functionality of the devices. Manufacturers believe that ensuring electromagnetic compatibility (EMC) in PCB design and using high EMC components is a luxury they cannot afford.

Many believe that EMC problems can be solved at the end of the development cycle with additional EMI suppression components. It is not always obvious that the cost of such corrections at the final stages of development will be many times higher than the costs of ensuring electromagnetic compatibility at the initial stages of design when creating a PCB. Thus, the desire to reduce the cost of materials and components will actually lead to a significant increase in the cost of the product.

To design a PCB with a low noise level and minimal sensitivity to interference, it is necessary, firstly, to properly organize the ground circuit, and secondly, to correctly arrange the printed circuit board. It is desirable for any PW to have a minimum ground impedance to ensure efficient current flow when interference occurs. On the other hand, it is a competent layout that is a prerequisite for creating a good printed circuit board. Proper routing not only reduces the impedance of the conductors, but also avoids common impedance coupling.

High Frequency PCB: Digital Circuits and Noise

Digital integrated circuits (ICs) containing logic gates are a source of transient noise due to transistor turn-off delays. Each time the logic gate changes state, a short pulse of through current flows through the complementary transistors of the output stage. The inductance of the ground traces does not allow the current to change abruptly, which leads to a voltage spike.

To reduce the effect of such interference, all digital circuits should have a minimum ground impedance. In addition, a decoupling component must be installed next to each logic chip, which ensures that the pulsed current loop does not propagate to the Vcc power supply.

The ground impedance can be reduced in several ways: by reducing the inductance of the conductive trace, by reducing the area of ​​the current loops, and by reducing the length of the paths carrying the current. This can be done in part by decoupling components located near each logic chip.

Reducing the inductance of earth conductors

The inductance of a conductor is directly proportional to its length. Therefore, it is necessary to reduce the length of the tracks along which the pulsed currents flow. An additional reduction in inductance is also possible by increasing the width of the power tracks. Unfortunately, the inductance is inversely proportional to the track width, and this approach is not very efficient. As a result, it is the track length that is the most important factor in terms of ensuring the minimum inductance.

If we neglect the mutual inductance, then the equivalent inductance of two identical parallel tracks will be half as much. In the case of four parallel tracks, the equivalent inductance will be four times less. However, there is a limit to using this approach. The fact is that if the tracks are close to each other, then the mutual inductance approaches the self-inductance, and the equivalent inductance does not decrease. However, if the traces are spaced twice their width apart, a 25% reduction in inductance can be achieved.

Thus, in a high-frequency circuit, you should provide as many alternative parallel paths as possible for the flow of earth currents. If the number of conductors is increased indefinitely, then we will eventually come to a layer of solid earth. Using a separate ground layer in multilayer boards allows you to solve a huge number of problems at once.

If we are talking about a two-layer board, then an acceptable result can be achieved by implementing the ground in the form of a grid (Fig. 1). In this case, the best option would be when the ground path passes under each microcircuit along its entire length. It is allowed to use a vertical grid spacing equal to the length of the IC. Vertical and horizontal traces can be on opposite sides of the board, but must be connected at grid nodes using vias.

Rice. 1. The earth is made in the form of a grid

It turned out that if in a conventional double-sided printed circuit board with 15 microcircuits the ground is made in the form of a grid, then the ground noise is reduced tenfold. Therefore, all double-layer printed circuit boards with digital ICs must use such a solution.

Reducing the area of ​​current loops

Another method for reducing inductance is to reduce the area of ​​current loops. A printed circuit board with a large open loop (Figure 2 a) is an effective noise generator. In addition, the circuit itself will also be sensitive to external magnetic fields.

Consider a power circuit consisting of two identical parallel traces—the Vcc supply trace and the GND ground trace—in which currents flow in opposite directions. Their total inductance (Lt) is calculated using formula 1:

Lt = 2 (L - M) (1)

where L is the inductance of each track and M is the mutual inductance.

If you place the Vcc and ground traces close together, the mutual inductance will be maximum, and the effective inductance will be almost halved. Ideally, on the PCB, the Vcc trace should run parallel to the ground trace. This reduces the area of ​​the current loop and helps to solve the problems associated with noise generation and sensitivity to interference.

On fig. 2a shows an unsuccessful layout of the printed circuit board, and in fig. 2b shows an improved version. In it, by reducing the circuit area, it was possible to reduce the length of the track and increase the mutual inductance, which made it possible to achieve a reduction in emissions and susceptibility to interference.

Decoupling Capacitors

On fig. 3 and the Vcc power and ground traces are close together. However, the path of the pulsed current, starting and ending at the power supply, forms a large loop (green area in the figure) that can generate electromagnetic interference. If a decoupling ceramic capacitor Cc, connected between the Vcc and ground circuits, is placed next to each IC, it acts as a buffer element to provide power to the IC during the switching time, thereby reducing the current flow loop.

Rice. 3. Decoupling capacitor

Ideally, the decoupling capacitor should be around 1 nF. Ceramic capacitors should be used because they are capable of discharging charge at a very high rate. High discharge current and low self-inductance make them ideal for power decoupling applications.

Impedance coupling in printed circuit boards

On fig. 4 shows an example of impedance coupling when using common power and ground rails. In this circuit, the analog amplifier shares the power and ground rails with the logic gate. Track impedances are shown as lumped elements (Zg and Zs). At higher frequencies, the impedances of the tracks increase many times over. This is not only due to an increase in the inductive component, but also due to an increase in resistance caused by the skin effect.

Rice. 4. Common impedance coupling

As we saw earlier, a voltage spike occurs whenever the logic gate switches. Part of the ground impedance (Zg3) is common to both the amplifier and the logic gate, so the amplifier will see this voltage pulse as noise in the power circuit. This noise can be transferred to the amplifier circuit either directly through the power input or through the common impedance Zg3. As a result, noise will appear directly at the input of the amplifier. To reduce the overall impedance coupling, either reduce the value of the overall impedance, or completely get rid of it.

Eliminate Common Impedance

Common impedance can be eliminated by star-connecting the power circuits of different circuits as shown in Figure 5. To do this, it is necessary to group the circuits depending on their own noise level and susceptibility to interference. Within each group, common buses can be used, but the power lines of individual groups are connected at one point. Such a connection is called a hybrid. The second approach is to use separate power supplies for each group of circuits, further improving isolation between circuits.

Rice. 5. Connection at one point

In this section, we consider how to avoid digital signal distortion associated with its transmission along the conductor on the printed circuit board. Although this is primarily a task for the circuit engineer, the PCB designer is also often to blame for signaling problems on the board, as well as the interference and crosstalk that occurs on the board.

Why is the signal distorted during transmission?
First of all, distortions are characteristic of high-frequency signals, with a frequency of 1 GHz or more. This is due to the effects of resonances and reflections on individual segments of conductors, vias, ramifications on the board, as well as at the inputs of receivers. However, the problem is that signals with frequencies up to 500 MHz, which are typical for standard digital circuits, as we will see below, can often be significantly distorted, which means that they can also be classified as high-frequency.

What is the idea of ​​transmission without distortion?
The principle of signal transmission without distortion is that the conductor is made as a transmission line (or "long line") with a given characteristic (wave) impedance, i.e. impedance Z 0 , the same throughout from the source to the receiver of the signal, which ensures the uniformity of the line. The second requirement is the consistency of the line with the source and receiver of the signal. Unlike a conventional conductor, such a transmission line does not lead to resonance, distortion and reflections during signal transmission, no matter how long it may be. Transmission lines can be easily implemented on a printed circuit board by using materials with known parameters and providing the required dimensions of the elements of the printed pattern. A distinction is made between series and parallel line matching, and it is necessary to use certain terminating resistors at the output of the source and / or the input of the signal receiver. Transmission lines formed on the board can, of course, be extended outside the board using connectors and cables with controlled impedance Z 0 .

For what signals does distortion become significant?
Comparing the length of the conductor on the board with the wavelength that the highest frequency component of the transmitted signal has (when propagating, for example, in FR4 material), one can determine the so-called electrical length of the conductor. The electrical length can be expressed in fractions of the minimum wavelength, or in fractions of its reciprocal, the front duration. If the conductor has too great an electrical length, then in order to prevent excessive signal distortion, this conductor must be made as a transmission line. Note that when transmitting high-frequency signals, transmission lines should be used not only to reduce distortion, but also to reduce the level of electromagnetic radiation (EMR).

Half Rise Rule
A rough rule of thumb is that a conductor is "electrically long" (what is called in electrical engineering "long line") if the signal rise time from the source to the farthest receiver exceeds half the signal rise time. It is in this case that reflections in the line can significantly distort the signal front. Assume that the device has chips with a rise time of 2 ns (for example, according to the documentation for the FastTTL series). The dielectric constant of the PCB material (FR4) at high frequencies is close to 4.0, which gives a front speed of about 50% of the speed of light, or 1.5.10 8 m/s. This corresponds to a front propagation time of 6.7 ps/mm. With this speed, the front will travel about 300 mm in 2 ns. From this we can conclude that for such signals, "transmission lines" should be used only if the length of the conductor exceeds half of this distance - that is, 150 mm.

Unfortunately, this is the wrong answer. The half-rise rule is overly simplistic and can lead to problems if its shortcomings are not taken into account.

Problems of the simplified approach
The data on the rise time given in the documentation for the microcircuits reflect the maximum value, and often the real switching time is significantly less (say, it can be 3-4 times less than the "maximum", and it can hardly be guaranteed that it will not vary from batch to batch of chips). Moreover, the unavoidable capacitive loading component (from the inputs of the microcircuits connected to the line) reduces the signal propagation speed compared to the calculated speed achievable on an empty printed circuit board. Therefore, to achieve adequate transmitted signal integrity, transmission lines should be used for much shorter conductors than the previously described rule suggests. It can be shown that for signals with a rise time (according to the documentation) of 2 ns, it is advisable to use transmission lines already for conductors whose length exceeds only 30 mm (and sometimes less)! This is especially true for signals that carry the function of synchronization or gating. It is for such signals that the problems associated with "false positive", "recalculation", "fixation of incorrect data" and others are typical.

How to design transmission lines?
There are many publications devoted to what types of transmission lines can be, how to design them on a printed circuit board, how to check their parameters. In particular, IEC 1188-1-2: 1988 provides detailed guidance on this. There are also many software products that allow you to choose the design of the transmission line and the structure of the printed circuit board. Most modern PCB design systems come with built-in programs that allow the designer to design transmission lines with given parameters. As an example, we can name such programs as AppCAD, CITS25, TXLine. The most complete possibilities are provided by software products from Polar Instruments.

Examples of transmission lines
As an example, consider the simplest types of transmission lines.

How to design a transmission line in the best way?
The highest speed (or most critical) signals should be in layers adjacent to the ground plan (GND), preferably the one that is paired with the decoupling power plan. Less critical signals can be routed to power plans if these plans are adequately decoupled and not very noisy. Each such power plan must be associated with the microcircuit from which or to which this signal is received. The best noise and EMC immunity is provided by striplines run between two GND plans, each paired with its own decoupling power plan.
The transmission line must not have holes, breaks or splits in any of the base plans against which it is drawn, as this leads to significant changes in Z 0 . Furthermore, the strip line should be as far away as possible from any gaps in the plan or from the edge of the reference plan, and this distance should not be less than ten times the width of the conductor. Adjacent transmission lines must be separated by at least three conductor widths to eliminate crosstalk. Very critical or "aggressive" signals (such as communication with a radio antenna) can benefit in EMC from using a balanced line with two rows of closely spaced vias, as if blocking it from other conductors and creating a coaxial structure in the printed circuit board. However, for such structures, Z 0 is calculated using other formulas.

How can the project be made cheaper?
The types of transmission lines described above almost always require the use of a multilayer board, so they may not be applicable to create mass products of the lower price category (although at high volumes 4-layer printed circuit boards are only 20-30% more expensive than double-sided ones). However, for low cost designs, line types such as balanced (uniform) or coplanar are also used, which can be constructed on a single layer board. It should be borne in mind that single-layer types of transmission lines occupy several times more area on the board than microstrip and strip lines. In addition, by saving on the cost of the PCB, you will be forced to pay more for additional device shielding and noise filtering. There is a general rule that it costs 10 to 100 times more to solve an EMC problem at the package level than to solve the same problem at the PCB level.
Therefore, when cutting your development budget by cutting back on the number of PCB layers, be prepared to spend extra time and money on multiple iterations of ordering sample boards to achieve the required level of signal integrity and EMC.

How to weaken the negative effect of changing layers?
According to the typical wiring rules, there is at least one decoupling capacitor near each microcircuit, so that we can change the layer near the microcircuit. However, the total length of the segments that are not located in the "strip" layer should be taken into account. A rough rule of thumb is that the total electrical length of these segments should not exceed one-eighth of the rise time. If too much change in Z 0 can occur on any of these segments (for example, when using ZIF sockets or other types of IC sockets), it is better to strive to minimize this length to one tenth of the rise time. Use the above rule to determine the maximum allowed total length of unnormalized segments and try to keep it as small as possible within these limits.
Based on this, for signals with a front time (according to the documentation) of 2 ns, we must change the layer no further than 10 mm from the center of the microcircuit or from the center of the terminating resistor. This rule is developed taking into account a 4-fold margin for the fact that the real switching time can be significantly less than the maximum according to the documentation. Approximately at the same distance (no more) from the place of layer change, there must be at least one decoupling capacitor connecting the corresponding ground and power plans. Such small distances are difficult to achieve when using large chips, so there are compromises in the layout of today's high-speed circuits. However, this rule justifies the preference for small chips in high-speed circuits, and explains the fact of the rapid development of BGA and flip-chip technologies, which minimize the signal path from the conductor on the board to the chip chip.

Modeling and testing prototypes
Due to the many variations of microcircuits and even more applications, some engineers may find these rules of thumb not precise enough, and some may find them exaggerated, but this is the role of "rules of thumb" - it is just a rough approximation that allows you to intuitively design correctly. working devices.
Nowadays, computer modeling tools are becoming more and more accessible and advanced. They allow you to calculate the parameters of signal integrity, EMC, depending on the actual layer structure and signal wiring. Of course, their application will give more accurate results than the use of our rough approximations, so we recommend using computer simulations as fully as possible. However, do not forget that the actual switching time of microcircuits can be significantly shorter than indicated in the documentation, and this can lead to incorrect results, so make sure that the model of the output and input stages corresponds to reality.
The next step is to check the passage of the critical signal on the first "prototype" PCB sample, using a high-frequency oscilloscope. Care must be taken to ensure that the waveform is not distorted as it travels along the PCB along the entire length of the conductor, and following the above rules alone is unlikely to give excellent results the first time, although they can be quite good. Using an RF Electromagnetic Field Analyzer, or Emission Spectrum Analyzer, can be another way to study signal integrity and EMC issues at the "prototype" PCB level. Methods of such analysis are not the subject of this article.
Even if you are using complex circuit simulation, don't neglect signal integrity and EMC testing on the earliest prototype PCBs.

Ensuring wave impedance at the stage of PCB manufacturing
A typical FR4 material intended for the manufacture of printed circuit boards has a dielectric constant value (E r) of about 3.8...4.2 per 1 GHz. Real values ​​of Er may vary within ±25%. There are vendor-specified and guaranteed E r4 materials available that are not much more expensive than conventional materials, but PCB manufacturers are not required to use "rated" FR4 grades unless specifically specified in the PCB order.
PCB manufacturers work with dielectrics of standard thicknesses (“prepregs” and “laminates”), and their thickness in each layer must be determined before the board is put into production, taking into account thickness tolerances (about ±10%). To provide a given Z 0 , for a certain thickness of the dielectric, you can choose the appropriate width of the conductor. For some manufacturers, it is necessary to indicate the actual required conductor width, for others - with a margin for undercut, which can reach 25-50 microns relative to the nominal width. The best option is to indicate to the manufacturer what width of the conductor in which layers is designed to ensure the specified Z 0 . In this case, the manufacturer can adjust the conductor width and layer structure to provide the specified parameters in accordance with its production technology. In addition, the manufacturer measures the actual wave impedance on each factory blank and rejects boards on which Z 0 does not fall within ±10% tolerance or more precisely.
For signals above 1 GHz it may be necessary to use higher frequency materials with better stability and other dielectric properties (such as Duroid from Rogers, etc.).

Literature
1. Design Techniques for EMC & Signal Integrity, Eur Ing Keith Armstrong.
2. IEC 61188-1-2: 1998 Printed Boards and Printed Board Assemblies - Design and use. Part 1-2: Generic Requirements - Controlled Impedance, www.iec.ch.
3. Design of multilayer printed circuit boards of high complexity. Seminar PCB technology, 2006.
4. http://library.espec.ws/books/chooseant/CHAPTER6/6-1.htm
5. Hardware design. Walt Kester.

GENERAL CONSIDERATIONS

Due to the significant differences between analog circuitry and digital circuitry, the analog part of the circuit must be separated from the rest of the circuit, and special methods and rules must be observed when wiring it. The effects of non-ideal PCB characteristics become especially noticeable in high-frequency analog circuits, but the general errors described in this article can affect the performance of devices operating even in the audio frequency range.

The intention of this article is to discuss common mistakes made by PCB designers, describe the impact of these mistakes on performance, and provide recommendations for resolving problems that arise.

Printed circuit board - circuit component

Only in rare cases can the printed circuit board of an analog circuit be routed so that the effects it introduces do not have any effect on the operation of the circuit. At the same time, any such impact can be minimized so that the characteristics of the device's analog circuitry are the same as those of the model and prototype.

Prototyping

Designers of digital circuits can correct small errors on the manufactured board by adding jumpers or, conversely, removing unnecessary conductors, making changes in the operation of programmable microcircuits, etc., moving on to the next design very soon. This is not the case for an analog circuit. Some of the common errors discussed in this article cannot be corrected by adding jumpers or removing excess wires. They can and will render the entire printed circuit board inoperable.

It is very important for a digital circuit designer using these correction methods to read and understand the material in this article well in advance of submitting the design to production. A little design attention and a discussion of possible options will not only prevent the PCB from becoming a scrap, but also reduce the cost due to blunders in a small analog part of the circuit. Finding bugs and fixing them can waste hundreds of hours. Prototyping can reduce this time to one day or less. Breadboard all your analog circuits.

Sources of noise and interference

Noise and interference are the main elements that limit the quality characteristics of circuits. Interference can be either emitted by sources or induced on circuit elements. Analog circuitry is often located on a printed circuit board along with high-speed digital components, including digital signal processors ( DSP).

High-frequency logic signals create significant RF interference ( RFI). The number of sources of noise emission is enormous: key power supplies for digital systems, mobile phones, radio and television, power supplies for fluorescent lamps, personal computers, lightning discharges, etc. Even if the analog circuit is operating in the audio frequency range, RFI can create noticeable noise in the output signal.

The choice of PCB design is an important factor in determining the mechanical performance of the device as a whole. For the manufacture of printed circuit boards, materials of various quality levels are used. The most suitable and convenient for the designer will be if the PCB manufacturer is located nearby. In this case, it is easy to control the resistivity and dielectric constant - the main parameters of the printed circuit board material. Unfortunately, this is not enough, and knowledge of other parameters such as flammability, high temperature stability, and hygroscopicity is often required. These parameters can only be known by the manufacturer of the components used in the production of printed circuit boards.

Layered materials are denoted by the indices FR ( flame resistant) and G. Material with index FR-1 has the highest flammability, and FR-5 has the lowest. Materials with indices G10 and G11 have special characteristics. The materials of printed circuit boards are given in Table. one.

Do not use category FR-1 printed circuit board. There are many examples of FR-1 PCBs that have been damaged by the heat of high power components. PCBs in this category are more like cardboard.

FR-4 is often used in the manufacture of industrial equipment, while FR-2 is used in the manufacture of household appliances. These two categories are industry standardized, and FR-2 and FR-4 circuit boards are often suitable for most applications. But sometimes the imperfection of the characteristics of these categories forces the use of other materials. For example, for very high frequency applications, PTFE and even ceramics are used as printed circuit board materials. However, the more exotic the PCB material, the higher the price can be.

When choosing a PCB material, pay special attention to its hygroscopicity, since this parameter can have a strong negative effect on the desired characteristics of the board - surface resistance, leakage, high-voltage insulating properties (breakdowns and sparks) and mechanical strength. Also pay attention to the operating temperature. Hot spots can be found in unexpected places, such as near large digital integrated circuits that switch at high frequency. If such areas are located directly below analog components, an increase in temperature can affect the characteristics of the analog circuit.

Table 1

	Components, comments
	paper, phenolic composition: pressing and stamping at room temperature, high hygroscopicity
	paper, phenolic composition: applicable for single-sided printed circuit boards of household appliances, low water absorption coefficient
	paper, epoxy composition: developments with good mechanical and electrical characteristics
	fiberglass, epoxy composition: excellent mechanical and electrical properties
	fiberglass, epoxy composition: high strength at elevated temperatures, non-flammable
	fiberglass, epoxy composition: high insulating properties, the highest strength of fiberglass, low hygroscopicity
	fiberglass, epoxy composition: high flexural strength at elevated temperatures, high solvent resistance

Once the PCB material is selected, the thickness of the PCB foil must be determined. This parameter is primarily selected based on the maximum value of the flowing current. If possible, try to avoid using very thin foil.

NUMBER OF LAYERS OF PRINTED BOARD

Depending on the overall circuit complexity and quality requirements, the designer must determine the number of PCB layers.

Single layer printed circuit boards

Very simple electronic circuits are made on single-sided boards using cheap foil materials (FR-1 or FR-2) and often have many jumpers, resembling double-sided boards. This way of creating printed circuit boards is recommended only for low-frequency circuits. For reasons to be described below, single-sided printed circuit boards are highly susceptible to interference . A good single-sided PCB is difficult to design for many reasons. Nevertheless, there are good boards of this type, but when developing them, you need to think a lot in advance.

Double layer printed circuit boards

At the next level are double-sided printed circuit boards, which in most cases use FR-4 as the substrate material, although sometimes FR-2 is also found. The use of FR-4 is more preferable, since holes are obtained from this material in printed circuit boards of better quality. Circuits on double-sided printed circuit boards are much easier to wire. in two layers, it is easier to route intersecting traces. However, trace crossing is not recommended for analog circuits. Where possible, the bottom layer ( bottom) must be placed under the ground polygon, and the rest of the signals should be placed in the upper layer ( top). Using a landfill as a ground bus provides several benefits:

• the common wire is the most frequently connected wire in the circuit; so it makes sense to have "a lot" of common wire to simplify wiring.
• increases the mechanical strength of the board.
• the resistance of all connections to the common wire is reduced, which, in turn, reduces noise and interference.
• the distributed capacitance for each circuit circuit is increased, helping to suppress radiated noise.
• the polygon, which is a screen, suppresses pickups emitted by sources located on the side of the polygon.

Double-sided printed circuit boards, despite all their advantages, are not the best, especially for small-signal or high-speed circuits. In general, the PCB thickness, i.e. the distance between the plating layers is 1.5 mm, which is too much to fully realize some of the advantages of a two-layer printed circuit board, given above. The allocated capacity, for example, is too small due to such a large spacing.

Multilayer printed circuit boards

Responsible circuit design requires multilayer printed circuit boards (MPBs). Some reasons for their use are obvious:

• the same convenient as for the common wire bus, power bus wiring; if polygons on a separate layer are used as power buses, then it is quite simple to supply power to each element of the circuit using vias;
• signal layers are freed from power rails, which facilitates the wiring of signal conductors;
• distributed capacitance appears between the ground and power polygons, which reduces high-frequency noise.

In addition to these reasons for using multilayer printed circuit boards, there are other less obvious ones:

• better suppression of electromagnetic ( EMI) and radio frequency ( RFI) interference due to the reflection effect ( image plane effect), known since the time of Marconi. When a conductor is placed close to a flat conducting surface, most of the return high frequency currents will flow in the plane directly below the conductor. The direction of these currents will be opposite to the direction of currents in the conductor. Thus, the reflection of the conductor in the plane creates a signal transmission line. Since the currents in the conductor and in the plane are equal in magnitude and opposite in direction, some reduction in radiated interference is created. Reflection effect works effectively only with non-breaking solid polygons (they can be both ground polygons and food polygons). Any breach of integrity will result in a reduction in interference suppression.
• reducing the overall cost in small-scale production. Even though multilayer printed circuit boards are more expensive to manufacture, their possible emission is less than that of single and double layer boards. Therefore, in some cases, the use of only multilayer boards will allow you to meet the requirements for radiation set during the development, and not to carry out additional tests and tests. The use of MFP can reduce the level of radiated noise by 20 dB compared to two-layer boards.

Layer order

For inexperienced designers, there is often some confusion about the optimal order of PCB layers. Take for example a 4-layer chamber containing two signal layers and two polygon layers - a ground layer and a power layer. What is the best layer order? Signal layers between polygons that will serve as screens? Or to make the polygon layers internal to reduce the interference of the signal layers?

It's important to remember in deciding this question that often the placement of layers doesn't really matter, because the components are on the outer layers anyway, and the busses that feed signals to their pins sometimes go through all the layers. Therefore, any screen effects are only a compromise. In this case, it is better to take care of creating a large distributed capacity between the power and ground polygons, placing them in the inner layers.

Another advantage of having the signal layers on the outside is the availability of signals for testing, as well as the possibility of modifying connections. Anyone who has ever changed the connections of conductors located in the inner layers will appreciate this opportunity.

For printed circuit boards with more than four layers, it is a general rule to place high-speed signal traces between the ground and power planes, and leave the outer layers for low-frequency ones.

GROUNDING

Good grounding is a common requirement for a rich, layered system. And it should be planned from the first step of design development.

Basic rule: division of the land .

Dividing the ground into analog and digital parts is one of the simplest and most effective methods of noise suppression. One or more layers of a multi-layer printed circuit board is usually allocated under a layer of ground planes. If the developer is not very experienced or careless, then the ground of the analog part will be directly connected to these polygons, i.e. the analog return current will use the same circuit as the digital return current. Auto breeders work in much the same way and unite all the lands together.

If a previously developed printed circuit board with a single ground polygon that combines analog and digital grounds is subjected to processing, then it is first necessary to physically separate the grounds on the board (after this operation, the operation of the board becomes almost impossible). After that, all connections are made to the analog ground plane of the analog circuit components (an analog ground is formed) and to the digital ground plane of the digital circuit components (the digital ground is formed). And only after that, the digital and analog grounds are combined in the source.

Other land formation rules:

Almost all clock signals are high enough frequency signals that even small capacitances between traces and polygons can create significant coupling. It must be remembered that not only the main clock frequency can cause a problem, but also its higher harmonics.

An example of good component placement

Figure 4 shows a possible layout of all components on the board, including the power supply. Three separate and isolated ground/power planes are used here: one for the source, one for the digital circuit, and one for the analog circuit. The ground and power circuits of the analog and digital parts are combined only in the power supply. High-frequency noise is filtered out in the supply circuits by chokes. In this example, the high frequency signals of the analog and digital parts are separated from each other. Such a design has a very high probability of a favorable outcome, since it ensures good placement of components and adherence to the rules of separation of circuits.

There is only one case where analog and digital signals need to be combined over an analog ground area. Analog-to-digital and digital-to-analog converters are housed in housings with analog and digital ground pins. Considering the previous considerations, it can be assumed that the digital ground pin and the analog ground pin should be connected to the digital and analog ground buses, respectively. However, this is not true in this case.

The pin names (analog or digital) refer only to the internal structure of the converter, to its internal connections. In the circuit, these pins should be connected to the analog ground bus. The connection can also be made inside the integrated circuit, however, it is rather difficult to obtain a low resistance of such a connection due to topological limitations. Therefore, when using converters, an external connection of the analog and digital ground pins is assumed. If this is not done, then the parameters of the microcircuit will be much worse than those given in the specification.

It must be taken into account that the digital elements of the converter can degrade the quality characteristics of the circuit, introducing digital noise into the analog ground and analog power circuits. The design of the converters takes this negative impact into account so that the digital part consumes as little power as possible. In this case, interference from switching logic elements is reduced. If the digital outputs of the converter are not heavily loaded, then internal switching usually does not cause much problems. When designing a printed circuit board containing an ADC or DAC, due consideration must be given to decoupling the converter's digital power to analog ground.

FREQUENCY CHARACTERISTICS OF PASSIVE COMPONENTS

Proper selection of passive components is essential for the correct operation of analog circuits. Begin your design development by carefully considering the high frequency characteristics of passive components and pre-positioning and arranging them on the board sketch.

A large number of designers completely ignore the frequency limitations of passive components when used in analog circuitry. These components have limited frequency ranges and their operation outside the specified frequency range can lead to unpredictable results. One might think that this discussion is only about high-speed analog circuits. However, this is far from being the case - high-frequency signals affect the passive components of low-frequency circuits quite strongly through radiation or direct connection through conductors. For example, a simple low-pass filter on an op-amp can easily turn into a high-pass filter when high frequency is applied to its input.

Resistors

The high frequency characteristics of the resistors can be represented by the equivalent circuit shown in Figure 5.

Usually three types of resistors are used: 1) wire, 2) carbon composite and 3) film. It doesn't take much imagination to understand how a wirewound resistor can turn into an inductance, since it is a coil of high resistance metal wire. Most electronic device designers have no idea about the internal structure of film resistors, which are also a coil, albeit made of a metal film. Therefore, film resistors also have an inductance that is less than that of wirewound resistors. Film resistors with a resistance of no more than 2 kOhm can be freely used in high-frequency circuits. The terminals of the resistors are parallel to each other, so there is a noticeable capacitive coupling between them. For high resistance resistors, terminal capacitance will reduce the overall impedance at high frequencies.

Capacitors

The high frequency characteristics of capacitors can be represented by the equivalent circuit shown in Figure 6.

Capacitors in analog circuits are used as decoupling and filtering components. For an ideal capacitor, the reactance is determined by the following formula:

Therefore, a 10µF electrolytic capacitor will have a resistance of 1.6Ω at 10kHz and 160µΩ at 100MHz. Is it so?

When using electrolytic capacitors, the correct connection must be observed. The positive terminal must be connected to a more positive DC potential. Incorrect connection leads to DC current flowing through the electrolytic capacitor, which can damage not only the capacitor itself, but also part of the circuit.

In rare cases, the DC potential difference between two points in a circuit can reverse sign. This requires the use of non-polar electrolytic capacitors, the internal structure of which is equivalent to two polar capacitors connected in series.

inductance

The high frequency characteristics of inductors can be represented by the equivalent circuit shown in Figure 7.

The reactance of an inductor is described by the following formula:

Therefore, a 10 mH inductor will have a reactance of 628 ohms at 10 kHz and a reactance of 6.28 MΩ at 100 MHz. Right?

Printed circuit board

The printed circuit board itself has the characteristics of the passive components discussed above, although not so obvious.

The pattern of conductors on a printed circuit board can be both a source and a receiver of interference. Good wiring reduces the sensitivity of the analog circuit to radiated sources.

The printed circuit board is susceptible to radiation because the conductors and leads of the components form a kind of antenna. Antenna theory is a fairly complex subject to study and is not covered in this article. However, some basics are given here.

A bit of antenna theory

At direct current or low frequencies, the active component predominates. As the frequency increases, the reactive component becomes more and more significant. In the range from 1 kHz to 10 kHz, the inductive component begins to take effect and the conductor is no longer a low-resistance connector, but rather acts as an inductor.

The formula for calculating the inductance of a PCB conductor is as follows:

Typically, PCB traces have values ​​between 6 nH and 12 nH per centimeter of length. For example, a 10 cm conductor has a resistance of 57 mΩ and an inductance of 8 nH per cm. At 100 kHz, the reactance becomes 50 mΩ, and at higher frequencies the conductor will be an inductance rather than a resistance.

The whip antenna rule states that it begins to noticeably interact with the field at its length of about 1/20 of the wavelength, and the maximum interaction occurs at the length of the pin, equal to 1/4 of the wavelength. Therefore, the 10 cm conductor from the example in the previous paragraph will start to become a pretty good antenna at frequencies above 150 MHz. It must be remembered that despite the fact that the clock generator of a digital circuit may not operate at a frequency higher than 150 MHz, higher harmonics are always present in its signal. If the PCB contains components with pin leads of considerable length, then these pins can also serve as antennas.

The other main type of antenna is the loop antenna. The inductance of a straight conductor increases greatly when it bends and becomes part of an arc. Increasing inductance lowers the frequency at which the antenna begins to interact with the field lines.

Experienced PCB designers who are fairly well versed in the theory of loop antennas know not to create loops for critical signals. Some designers, however, do not think about this, and the return and signal current conductors in their circuits are loops. The creation of loop antennas is easy to show with an example (Fig. 8). In addition, the creation of a slot antenna is shown here.

Consider three cases:

Option A is an example of bad design. It does not use the analog ground polygon at all. The loop circuit is formed by a ground and signal conductor. When a current passes, an electric field and a magnetic field perpendicular to it arise. These fields form the basis of a loop antenna. The loop antenna rule states that for maximum efficiency, the length of each conductor should be equal to half the wavelength of the received radiation. However, one should not forget that even at 1/20 of the wavelength, the loop antenna is still quite effective.

Option B is better than option A, but there is a gap in the polygon, probably to create a specific place for the signal wires to be routed. The signal and return current paths form a slot antenna. Other loops are formed in the cutouts around the chips.

Option B is an example of a better design. The signal and return current paths overlap, negating the efficiency of the loop antenna. Note that this option also has cutouts around the ICs, but they are separated from the return current path.

The theory of reflection and matching of signals is close to the theory of antennas.

When the PCB conductor is rotated through 90°, reflections can occur. This is mainly due to the change in the width of the current path. At the top of the corner, the trace width increases by a factor of 1.414, which leads to a mismatch in the characteristics of the transmission line, especially the distributed capacitance and the intrinsic inductance of the trace. Quite often it is necessary to rotate a trace 90° on a PCB. Many modern CAD packages allow you to smooth the corners of the drawn paths or draw the paths in the form of an arc. Figure 9 shows two steps to improve the corner shape. Only the last example keeps the trace width constant and minimizes reflections.

Tip for experienced PCB layoutrs: leave the smoothing procedure to the last stage of work before creating droplets and pouring polygons. Otherwise, the CAD package will take longer to smooth due to more complex calculations.

PCB traces on different layers are capacitively coupled when they cross. Sometimes this can create a problem. Conductors stacked on top of each other on adjacent layers create a long film capacitor. The capacitance of such a capacitor is calculated according to the formula shown in Figure 10.

For example, a printed circuit board may have the following parameters:
- 4 layers; signal and ground polygon layer are adjacent,
- interlayer interval - 0.2 mm,
- conductor width - 0.75 mm,
- conductor length - 7.5 mm.

Typical ER value for FR-4 is 4.5.

Substituting all the values ​​into the formula, we get the capacitance value between these two buses, equal to 1.1 pF. Even such a seemingly small capacity is unacceptable for some applications. Figure 11 illustrates the effect of a 1 pF capacitance when connected to the inverting input of a high frequency op amp.

It can be seen that the output signal amplitude doubles at frequencies close to the upper limit of the OS frequency range. This, in turn, can lead to generation, especially at antenna operating frequencies (above 180 MHz).

This effect gives rise to numerous problems, for which, nevertheless, there are many ways. The most obvious of these is the reduction in the length of the conductors. Another way is to reduce their width. There is no reason to use a conductor of this width to feed the signal to the inverting input, since Very little current flows through this conductor. Reducing the trace length to 2.5 mm and the width to 0.2 mm will reduce the capacitance to 0.1 pF, and such a capacitance will no longer lead to such a significant increase in the frequency response. Another way to solve it is to remove part of the polygon under the inverting input and the conductor coming up to it.

The width of PCB traces cannot be reduced indefinitely. The limiting width is determined by both the technological process and the thickness of the foil. If two conductors pass close to each other, then a capacitive and inductive coupling is formed between them (Fig. 12).

Signal wires should not be run parallel to each other, except in the case of differential or microstrip wiring. The gap between the conductors must be at least three times the width of the conductors.

Capacitance between traces in analog circuits can be problematic for large resistor values ​​(several MΩ). The relatively large capacitive coupling between the inverting and non-inverting inputs of an op-amp can easily cause the circuit to self-excite.

For example, with d=0.4 mm and h=1.5 mm (quite common values), the inductance of the hole is 1.1 nH.

Remember that if there are large resistances in the circuit, then special attention should be paid to cleaning the board. Flux residues and contaminants must be removed during the final stages of PCB fabrication. Recently, when mounting printed circuit boards, water-soluble fluxes are often used. Being less harmful, they are easily removed with water. But at the same time, washing the board with insufficiently clean water can lead to additional contamination, which worsens the dielectric characteristics. Therefore, it is very important to clean the PCB with high impedance circuitry with fresh distilled water.

SIGNAL INTERCOUPLING

As already noted, noise can enter the analog part of the circuit through the power circuits. To reduce such interference, decoupling (blocking) capacitors are used to reduce the local impedance of the power buses.

If you need to separate a printed circuit board that has both analog and digital parts, then you need to have at least a little idea about the electrical characteristics of logic elements.

A typical output stage of a logic element contains two transistors connected in series with each other, as well as between the power and ground circuits (Fig. 14).

These transistors ideally operate strictly in antiphase, i.e. when one of them is open, then at the same time the second one is closed, generating either a logical one or a logical zero signal at the output. In the steady-state logic state, the power consumption of the logic element is small.

The situation changes dramatically when the output stage switches from one logic state to another. In this case, for a short period of time, both transistors can be opened simultaneously, and the supply current of the output stage increases greatly, since the resistance of the section of the current path from the power bus to the ground bus through two series-connected transistors decreases. The power consumption increases abruptly and then also decreases, which leads to a local change in the supply voltage and the appearance of a sharp, short-term change in current. Such current changes result in the emission of RF energy. Even on a relatively simple printed circuit board, there may be dozens or hundreds of considered output stages of logic elements, so the total effect of their simultaneous operation can be very large.

It is impossible to accurately predict the frequency range over which these current surges will occur, since the frequency of their occurrence depends on many factors, including the propagation delay of switching transistors in the logic element. The delay, in turn, also depends on many random causes that occur during the production process. Switching noise has a broadband harmonic distribution over the entire range. To suppress digital noise, there are several methods, the application of which depends on the spectral distribution of the noise.

Table 2 lists the maximum operating frequencies for common capacitor types.

table 2

From the table it is obvious that tantalum electrolytic capacitors are used for frequencies below 1 MHz, at higher frequencies ceramic capacitors should be used. It must be remembered that capacitors have their own resonance and the wrong choice of them can not only not help, but also exacerbate the problem. Figure 15 shows typical self-resonances of two general purpose capacitors, a 10 µF tantalum electrolytic and a 0.01 µF ceramic.

Actual specifications may vary from manufacturer to manufacturer and even from lot to lot from the same manufacturer. It is important to understand that for the capacitor to work effectively, the frequencies it suppresses must be in a lower range than the self-resonant frequency. Otherwise, the nature of the reactance will be inductive, and the capacitor will no longer work effectively.

Make no mistake that a single 0.1uF capacitor will reject all frequencies. Small capacitors (10 nF or less) can work more efficiently at higher frequencies.

IC Power Decoupling

Integrated circuit power decoupling to suppress high frequency noise consists of one or more capacitors connected between the power and ground pins. It is important that the conductors connecting the leads to the capacitors are kept short. If this is not the case, then the self-inductance of the conductors will play a significant role and negate the benefits of using decoupling capacitors.

A decoupling capacitor must be connected to each chip package, regardless of whether there are 1, 2, or 4 opamps inside the package. If the op-amp is powered by a bipolar supply, then it goes without saying that decoupling capacitors must be located at each power pin. The capacitance value must be carefully chosen depending on the type of noise and interference present in the circuit.

In particularly difficult cases, it may be necessary to add an inductor connected in series with the power output. The inductance should be placed before, not after, the capacitors.

Another, cheaper way is to replace the inductance with a low resistance resistor (10 ... 100 ohms). In this case, together with the decoupling capacitor, the resistor forms a low-frequency filter. This method reduces the supply range of the op-amp, which also becomes more dependent on power consumption.

Usually, to suppress low-frequency noise in power circuits, it is sufficient to use one or more aluminum or tantalum electrolytic capacitors at the power input connector. An additional ceramic capacitor will suppress high frequency noise from other boards.

INPUT AND OUTPUT DEPOSIT

Many noise problems result from directly connecting input and output pins. As a result of the high-frequency limitations of passive components, the circuit's response to exposure to high-frequency noise can be quite unpredictable.

In a situation where the frequency range of the induced noise is significantly different from the frequency range of the circuit, the solution is simple and obvious - to place a passive RC filter to suppress high-frequency noise. However, when using a passive filter, one must be careful: its characteristics (due to the non-ideal frequency characteristics of passive components) lose their properties at frequencies that are 100 ... 1000 times higher than the cutoff frequency (f 3db). When using series-connected filters tuned to different frequency ranges, the higher-pass filter should be closest to the interferer. Ferrite inductors can also be used for noise suppression; they retain the inductive nature of the resistance up to a certain specific frequency, and above their resistance becomes active.

The interference on the analog circuit can be so great that it is possible to get rid of (or at least reduce) it only by using screens. To work effectively, they must be carefully designed so that the frequencies that cause the most problems cannot enter the circuit. This means that the shield must not have holes or cutouts larger than 1/20 of the wavelength of the shielded radiation. It is a good idea to allow enough space for the intended screen from the very beginning of the PCB design. When using a shield, you can additionally use ferrite rings (or beads) for all connections to the circuit.

OP-AMP BODIES

One case usually houses one, two or four operational amplifiers (Fig. 16).

A single op-amp often also has additional inputs, for example to adjust the bias voltage. Dual and quad op amps have only inverting and non-inverting inputs and outputs. Therefore, if you need to have additional adjustments, you must use single operational amplifiers. When using additional outputs, it must be remembered that they are auxiliary inputs in their structure, therefore, they must be managed carefully and in accordance with the manufacturer's recommendations.

In a single op-amp, the output is located on the opposite side of the inputs. This can make it difficult to operate the amplifier at high frequencies due to the length of the feedback wires. One way to overcome this is to place the amplifier and feedback components on opposite sides of the PCB. This, however, results in at least two additional holes and cutouts in the ground polygon. Sometimes it is worth using a dual op-amp to solve this problem, even if the second amplifier is not used (and its outputs must be connected properly). Figure 17 illustrates the shortening of the feedback loop wires for an inverting connection.

Dual op amps are especially common in stereo amplifiers, and quad op amps in multi-stage filter circuits. However, this has a rather significant downside. Although current technology provides decent isolation between the signals of amplifiers located on the same silicon chip, there is still some crosstalk between them. If it is necessary to have a very small amount of such interference, then it is necessary to use single operational amplifiers. Crosstalk does not only occur with dual or quad amplifiers. Their source can be a very close location of the passive components of different channels.

Dual and quad op amps, in addition to the above, allow for tighter mounting. Separate amplifiers are, as it were, mirrored relative to each other (Fig. 18).

Figures 17 and 18 do not show all of the connections required for normal operation, such as a midrange driver with a single supply. Figure 19 shows a diagram of such a driver when using a quad amplifier.

The diagram shows all the necessary connections for the implementation of three independent inverting stages. It is necessary to pay attention to the fact that the conductors of the half-voltage driver are located directly under the integrated circuit package, which makes it possible to reduce their length. This example illustrates not how it should be, but what should be done. The mid-level voltage, for example, could be the same for all four amplifiers. Passive components can be appropriately sized. For example, size 0402 planar components match the pin spacing of a standard SO package. This allows very short conductor lengths for high frequency applications.

VOLUMETRIC AND SURFACE MOUNTING

When placing operational amplifiers in DIP packages and passive components with wire leads, the presence of vias on the printed circuit board is required for their installation. Such components are currently used when there are no special PCB size requirements; they are usually cheaper, but the cost of the printed circuit board increases during the manufacturing process due to drilling additional holes for component leads.

In addition, when using add-on components, the dimensions of the board and the length of the conductors increase, which does not allow the circuit to operate at high frequencies. The vias have their own inductance, which also imposes restrictions on the dynamic characteristics of the circuit. Therefore, plug-in components are not recommended for high-frequency circuits or for analog circuits located near high-speed logic circuits.

Some designers, in an attempt to reduce the length of the conductors, place the resistors vertically. At first glance, it may seem that this reduces the length of the route. However, this increases the current path through the resistor, and the resistor itself is a loop (coil of inductance). The radiating and receiving capacity increases many times over.

Surface mount does not require a hole for each pin of the component. However, there are problems when testing a circuit, and you have to use vias as test points, especially when using small-scale components.

UNUSED OU SECTIONS

When using dual and quad op amps in the circuit, some of their sections may remain unused and must be connected correctly in this case. Incorrect connection can lead to an increase in power consumption, more heat and more noise used in the same package of op-amps. The outputs of unused operational amplifiers can be connected as shown in fig. 20a. Connecting pins with additional components (Fig. 20b) will make it easy to use this op-amp during commissioning.

CONCLUSION

Keep the following key points in mind and keep them in mind when designing and wiring analog circuits.

General:

• think of the printed circuit board as an electrical circuit component;
• have an idea and understanding of the sources of noise and interference;
• model and layout circuits.

Printed circuit board:

• use printed circuit boards only from high-quality material (for example, FR-4);
• circuits made on multilayer printed circuit boards are 20 dB less susceptible to external interference than circuits made on two-layer boards;
• use separate, non-overlapping polygons for different lands and feeds;
• place the ground and power polygons on the inner layers of the PCB.

Components:

• be aware of the frequency limitations introduced by the board's passive components and traces;
• try to avoid vertical placement of passive components in high speed circuits;
• for high-frequency circuits, use components designed for surface mounting;
• conductors should be the shorter the better;
• if a longer conductor length is required, then reduce its width;
• unused leads of active components must be properly connected.

Wiring:

• place the analog circuit near the power connector;
• never route wires carrying logic signals through the analog area of ​​the board, and vice versa;
• make the conductors suitable for the inverting input of the op-amp short;
• make sure that the conductors of the inverting and non-inverting inputs of the op-amp are not parallel to each other for a long distance;
• try to avoid using extra vias, because their own inductance can lead to additional problems;
• do not run conductors at right angles and smoothen the tops of the corners if possible.

Interchange:

• use the correct types of capacitors to suppress noise in power circuits;
• to suppress low-frequency interference and noise, use tantalum capacitors at the power input connector;
• to suppress high-frequency interference and noise, use ceramic capacitors at the power input connector;
• use ceramic capacitors at each power output of the microcircuit; if necessary, use several capacitors for different frequency ranges;
• if excitation occurs in the circuit, then it is necessary to use capacitors with a smaller capacitance value, and not a larger one;
• in difficult cases in power circuits, use series-connected resistors of small resistance or inductance;
• analog power decoupling capacitors should only be connected to analog ground, not digital ground.

When designing printed circuit boards with cost optimization, a number of key issues arise. While the initial goal may be to design the PCB as small as possible, it may not be the cheapest solution for the entire system. Reducing PCB size is possible by increasing the number of PCB layers, which in turn introduces EMC issues that can result in huge project costs.

Electromagnetic Interference, EMI or Electromagnetic Compatibility, EMC is a key factor in PCB design. Ensuring the electromagnetic compatibility of the device as a whole can be an extremely costly process if the designer "cut corners" in the design and manufacture of printed circuit boards, so some cost-cutting approaches should be discarded at the very beginning. If the components will interact with EMI or emit EMI, it will require high costs in order to meet the EMC requirements during the test phase.

While a four-layer board is considered to be the optimal balance of EMI protection and board routing, it is often possible to design a two-layer board with the same characteristics using free PCB routing tools such as DesignSpark PCB. This provides a significant reduction in the cost of manufacturing a printed circuit board without affecting the course of tests in the future.

Signal return paths are the most difficult problem in PCB routing. It would be quite difficult to trace the return ground under each trace associated with the signal pin of the microcontroller, but this is exactly what a four-layer ground-layer board provides. It doesn't matter where the traces go, there is always a return signal path to ground underneath them.

The closest to the ground layer in terms of characteristics on a two-layer board is the ground grid, which reduces the emission of electromagnetic interference from the signal tracks. Reducing the area of ​​the loop by routing the return path under the signal trace is the most efficient way to solve this problem, and creating a ground grid is the most important step (after layout planning) in PCB routing.

Lattice generation creates a surface

Lattice generation is a key technique for achieving EMC in dual layer boards. Much like a power network, it is a network of rectangular connections between grounded conductors. In effect, this creates a ground plane that provides the same EMI reduction as a 4-layer board and effectively emulates the ground plane used in a 4-layer board to improve EMC, creating a return path to ground under each signal trace and reducing the impedance between the microcontroller and voltage regulator.

Grid generation is performed by extending ground traces and creating grounded conductive flat figures in order to create a network of ground connections across the PCB surface. For example, if a PCB has predominantly top layer traces running vertically and bottom layer traces running predominantly horizontal, this already worsens the conditions for routing return paths to ground under the signal traces, which is usually done in two steps:

• first, all ground conductors are expanded in order to take up the largest space on the printed circuit board;
• then all the remaining free space is filled with a grounded surface.

The goal of this approach is to generate as large a grid as possible on a two-layer printed circuit board. Small changes to the PCB layout may allow additional connections to increase the area of ​​the ground grid.

PCB zoning

PCB zoning is another technology that can be used to reduce PCB noise and EMI and thus reduce the need for additional PCB layers. This technique has the same basic meaning as component placement planning, which is the process of locating components on a blank board before routing traces. PCB zoning is a slightly more complex process of placing similar functionality in the same PCB zone, rather than mixing functionally different components together. High-speed logic, including microcontrollers, is placed as close as possible to the power circuits, slow components are placed further, and analog components are further away. This approach significantly affects the EMC of the printed circuit board.

With this arrangement, high-speed logic has less effect on the conductors of other signals. It is especially important that the crystal loop be placed away from analog circuits, low speed signals and connectors. This rule applies to printed circuit boards as well as to the placement of components inside the device. Layouts where cable bundles are placed around a resonator or microcontroller should be avoided, as these cables will pick up noise and carry it everywhere. Thus, during zoning, the placement of connectors on the printed circuit board is also determined.

PCB Development Tools

There are many development tools available to support design with EMC optimization in mind. One of these means DesignSpark PCB is the latest version that supports design rules checking (DRC) when tracing, rather than when checking after tracing is complete. This is especially useful when optimizing a PCB for cost, as any conflicts or errors are immediately signaled and can be resolved. Of course, these checks depend on the completeness of the information given by the designer, but this approach allows you to speed up the routing process and thus free up time for other important issues.

Version 5 DesignSpark PCB Online Design Rule Check checks any components that have been added and moved as a result of interactive editing operations. For example, all wires attached to a moved component and all wires added during manual routing are checked.

Version 5 also added bus support so that traces can be easily grouped and routed together. Instead of drawing all the connections in a design and connecting them to each pin, the designer can create a less cluttered design with busses by adding component pin connections to the bus through which the signal is passed.

Figure 1: Adding Busbars to DesignSpark PCB Version 5

Tires can be open or closed. A closed bus is a collection of wire names predefined for a given bus, and only those wires can connect to a given bus, while an open bus can include any wire.

While these features make sense when routing busbars, they can be used to route other traces on a PCB. This ability to use busbars in circuits can help make the design simpler and clearer by grouping multiple EMI emitting conductors together with their surrounding ground return conductors and thereby reducing EMI on the board being designed. A good rule of thumb is never to run EMI emitting traces on the outside of the board, which can be tricky for small two-layer boards. Keeping non-EMI circuits away from locations such as connectors, resonator circuits, relays, relay drivers, where EMI can be induced in these circuits also helps to improve electromagnetic compatibility.

Conclusion

Designing a PCB with the simplicity required to reduce cost is perhaps more of a challenge than exploiting the richness of a multilayer board.

Some EMC problems can be solved by using coupling capacitors and ferrite beads to suppress any signals that may be emitted, but this adds complexity to the design and increases the cost of production. While EMI and EMC problems can be minimized with the right design rules using zoning and crosstalk considerations, power and ground grid generation can provide the same level of shielding in a two-layer board that is possible in a four- or six-layer design. This not only reduces the cost of manufacturing the board, but also improves reliability and performance, including electromagnetic compatibility, thus reducing the life cycle cost of the equipment.