Converting analog information into digital form. What is ACP

- an electronic circuit that receives two analog signals at its inputs and outputs a logical "0" or "1", depending on which of the signals is larger.

The two analog inputs are named non-inverting(+) and inverting (-). If the voltage at the non-inverting input is greater than at the inverting input, the output signal is equal to logic "1", otherwise - to logic "0".
When enabled, the comparator allows you to compare the voltage values ​​present at the corresponding inputs of the microcontroller.
The result of the comparison is a boolean value that can be read within the program. Based on the result of the comparison, an interrupt can be generated, and the state of the timer-counter can also be captured.
In order for microcontroller pins with the appropriate alternative function to be used as an analog comparator, they must be configured as analog inputs.

Analog to digital converter

Analog to digital converter(ADC) is a device that converts an input analog signal into a discrete code (digital signal), most often binary. The reverse transformation is carried out using digital-to-analogue converter(DAC).
Any physical continuously changing quantity or its equivalent can act as an analog signal. Most often, an equivalent voltage signal is used as an input signal to obtain digital information about temperature, current, humidity, etc.
Most analog-to-digital converters are linear, meaning that the range of input values ​​mapped to an output digital value is linearly related to that output value. The basis for building an ADC is an analog comparator.
ADC resolution is the minimum change in the value of an analog signal that can be converted by a given ADC. Usually measured in volts.


The bit depth of the ADC characterizes the number of discrete values ​​that the converter can produce at the output. Measured in bits. For example, an ADC capable of outputting 2 8 =256 discrete values ​​(0..255), has a capacity of 8 bits.
equals the difference between the voltages corresponding to the maximum and minimum output code, divided by the number of output discrete values.

where N- bit depth of the ADC.
In this case, the voltage at the input of the converter can be estimated knowing the obtained digital value of the analog-to-digital conversion value

In practice, the resolution of an ADC is limited by the signal-to-noise ratio of the input signal. With a high noise intensity at the ADC input, it becomes impossible to distinguish adjacent levels of the input signal, that is, the resolution deteriorates. In this case, the actually achievable resolution is described effective bit depth(effective number of bits - ENOB), which is less than the actual bit depth of the ADC. When converting a highly noisy signal, the lower bits of the output code are practically useless, since they contain noise.

Signal sampling is called the measurement conversion of a continuous signal x(t) into the sequence of instantaneous values ​​of this signal X(k i T) corresponding to certain points in time k i T (T is the sampling step).


The signal discretization in time can be carried out with a constant step T= const or variable step T= var.

Sampling frequency– the frequency with which the analog-to-digital signal conversion is performed.
Conversion time is the time from the beginning of the conversion to the appearance of the corresponding code at the ADC output.
Reference voltage is the voltage corresponding to the maximum output code.

Since real ADCs cannot perform A/D conversion instantaneously, the analog input value must be held constant at least from the beginning to the end of the conversion process (this time interval is called conversion time). This problem can be solved by using a special circuit at the input of the ADC - sample-hold devices(UVH). The SHA usually stores the input voltage in a capacitor, which is connected to the input via an analog switch: when the switch is closed, the input signal is sampled (the capacitor is charged to the input voltage), and when the switch is opened, it is stored. As a rule, ADC modules contain a built-in SHA.

The article describes the device and principles of operation of analog-to-digital converters of various types, as well as their main characteristics, indicated by manufacturers in the documentation.

The analog-to-digital converter (ADC) is one of the most important electronic components in measurement and test equipment. The ADC converts the voltage (analog signal) into a code, on which the microprocessor and software perform certain actions. Even if you only work with digital signals, you are most likely using an ADC on your oscilloscope to find out their analog characteristics.

There are several basic types of ADC architecture, although there are also many variations within each type. Different types of measurement equipment use different types of ADCs. For example, a digital oscilloscope uses a high sample rate but does not require high resolution. Digital multimeters need more resolution, but you can sacrifice measurement speed. General purpose data acquisition systems typically rank between oscilloscopes and digital multimeters in terms of sample rate and resolution. This type of equipment uses a successive approximation ADC or a sigma-delta ADC. There are also parallel ADCs for applications requiring high-speed analog signal processing and integrating ADCs with high resolution and noise reduction.

In Fig.1. the capabilities of the main ADC architectures are shown depending on the resolution and sampling rate.

Rice. 1. Types of ADC - resolution depending on the sampling rate

Parallel ADCs

Most high-speed oscilloscopes and some high-frequency instruments use parallel ADCs because of their high conversion speed, which can reach 5 Hz (5 x 10 9) samples/sec for standard devices and 20 Hz samples/sec for original designs. Parallel ADCs typically have a resolution of up to 8 bits, but 10-bit versions are also available.

Rice. 2. ADC parallel conversion

Rice. 2 shows a simplified block diagram of a 3-bit parallel ADC (for converters with higher resolution, the principle of operation is the same). It uses an array of comparators, each of which compares the input voltage to an individual reference voltage. Such a reference voltage for each comparator is formed on the built-in precision resistive divider. The voltage references start at half the least significant digit (LSB) and increase with each successive comparator in increments of V REF /2 3 . As a result, a 3-bit ADC requires 2 3 -1 or seven comparators. And, for example, for an 8-bit parallel ADC, 255 (or (2 8 -1)) comparators will be required.

As the input voltage increases, the comparators sequentially set their outputs to logic one instead of logic zero, starting with the comparator responsible for the least significant bit. You can imagine the converter as a mercury thermometer: as the temperature rises, the mercury column rises. On fig. 2, the input voltage falls between V3 and V4, so the bottom 4 comparators output "1" and the top three comparators output "0". The decoder converts (2 3 -1) - bit digital word from the outputs of the comparators into a binary 3-bit code.

Parallel ADCs are reasonably fast devices, but they have their drawbacks. Due to the need to use a large number of comparators, parallel ADCs consume significant power and are not practical for battery-powered applications.

When a resolution of 12, 14, or 16 bits is needed and high conversion speed is not required, and low price and low power consumption are the determining factors, successive approximation ADCs are usually used. This type of ADC is most commonly used in a variety of instrumentation and data acquisition systems. At the moment, successive approximation ADCs allow measuring voltage with an accuracy of up to 16 bits with a sampling rate from 100K (1x10 3) to 1M (1x10 6) samples/sec.

Rice. 3 shows a simplified block diagram of a successive approximation ADC. This type of ADC is based on a special successive approximation register. At the beginning of the conversion cycle, all outputs of this register are set to logic 0, except for the first (highest) bit. This generates a signal at the output of the internal digital-to-analog converter (DAC) whose value is equal to half the input range of the ADC. And the output of the comparator switches to a state that determines the difference between the signal at the DAC output and the measured input voltage.

Rice. 3. SAR ADC

For example, for an 8-bit SAR ADC (Figure 4), the register outputs are set to "10000000". If the input voltage is less than half the input range of the ADC, then the output of the comparator will be logic 0. This instructs the successive approximation register to switch its outputs to the state "01000000", which will accordingly change the output voltage from the DAC to the comparator. If the comparator output would still remain at "0", then the register outputs would switch to the state "00100000". But at this conversion cycle, the output voltage of the DAC is less than the input voltage (Fig. 4), and the comparator switches to a logic 1 state. This instructs the successive approximation register to store a "1" in the second bit and apply a "1" to the third bit. The described operation algorithm is then repeated again until the last digit. Thus, a successive approximation ADC requires one internal conversion clock per bit, or N clocks for an N-bit conversion.

Rice. 4. Conversion to ADC of successive approximations

However, the operation of the successive approximation ADC has a peculiarity associated with transients in the internal DAC. Theoretically, the voltage at the output of the DAC for each of the N internal conversion cycles should be set in the same period of time. But in fact, this interval in the first bars is much larger than in the last ones. Therefore, the conversion time of a 16-bit successive approximation ADC is more than twice the conversion time of an 8-bit successive approximation ADC.

Most measurements often do not require an ADC with the conversion speed that a successive approximation ADC provides, but a high resolution is needed. Sigma-delta ADCs can provide up to 24 bits of resolution, but are inferior in conversion speed. So, in a sigma-delta ADC at 16 bits, you can get a sampling rate of up to 100K samples/sec, and at 24 bits this frequency drops to 1K samples/sec or less, depending on the device.

Typically, sigma-delta ADCs are used in a variety of data acquisition systems and in measuring equipment (measurement of pressure, temperature, weight, etc.) when a high sampling rate is not required and a resolution of more than 16 bits is required.

The principle of operation of the sigma-delta ADC is more difficult to understand. This architecture belongs to the class of integrating ADCs. But the main feature of the sigma-delta ADC is that the sampling frequency, at which the voltage level of the measured signal is actually analyzed, significantly exceeds the sampling rate at the ADC output (sampling frequency). This sampling rate is called the resampling rate. For example, a sigma-delta ADC with a conversion rate of 100K samples/sec, which uses a resampling rate of 128 times faster, will sample the input analog signal at a rate of 12.8M samples/sec.

The block diagram of the first-order sigma-delta ADC is shown in fig. 5. An analog signal is applied to an integrator whose outputs are connected to a comparator, which in turn is connected to a 1-bit DAC in a feedback loop. Through a series of successive iterations, the integrator, comparator, DAC, and adder produce a stream of serial bits that contains information about the magnitude of the input voltage.

Rice. 5. Sigma-Delta ADC

The resulting digital sequence is then fed to a low-pass filter to suppress components above the Kotelnikov frequency (half the ADC sample rate). After removing the high-frequency components, the next node - the decimator - thins out the data. In the ADC we are considering, the decimator will leave 1 bit out of every 128 received in the output digital sequence.

Since the internal digital low-pass filter in the sigma-delta ADC is an integral part of the conversion process, the low-pass filter settling time becomes a factor to consider when hopping the input signal. For example, when switching the input multiplexer or when switching the measurement limit of the device, it is necessary to wait until several ADC samples have passed, and only then read the correct output data.

An additional and very important advantage of the sigma-delta ADC is that all its internal units can be made integrally on the area of ​​one silicon chip. This significantly reduces the cost of end devices and increases the stability of the ADC characteristics.

Integrating ADCs

And the last type of ADC that will be discussed here is the push-pull ADC. In digital multimeters, as a rule, just such ADCs are used, because. these instruments require a combination of high resolution and high noise suppression. The idea of ​​conversion in such an integrating ADC is much less complicated than in a sigma-delta ADC.

Figure 6 shows how a push-pull ADC works. The input signal charges the capacitor for a fixed period of time, which is usually one cycle of the mains frequency (50 or 60 Hz) or a multiple of it. When integrating the input signal over a period of time of this duration, high-frequency noise is suppressed. At the same time, the influence of voltage instability of the mains power supply on the conversion accuracy is eliminated. This is because the value of the integral of the sinusoidal signal is zero if the integration is carried out over a time interval that is a multiple of the period of the sinusoidal change.

Rice. 6. Integrating ADC. Green color shows interference from the mains (1 period)

At the end of the charge time, the ADC discharges the capacitor at a fixed rate, while an internal counter counts the number of clock pulses during the discharge of the capacitor. A longer discharge time therefore corresponds to a larger meter reading and a larger measured voltage (Fig. 6).

Push-pull ADCs have high accuracy and high resolution, and also have a relatively simple structure. This makes it possible to implement them in the form of integrated circuits. The main disadvantage of such ADCs is the long conversion time, due to the binding of the integration period to the duration of the power supply period. For example, for 50 Hz equipment, the sampling rate of the push-pull ADC does not exceed 25 samples/sec. Of course, such ADCs can also work with a higher sampling rate, but as the latter increases, the noise immunity decreases.

ADC specification

There are general definitions that are commonly used in relation to analog-to-digital converters. However, the specifications given in the technical documentation of ADC manufacturers can seem rather confusing. The correct choice of the ADC that is optimal in terms of its characteristics for a particular application requires an accurate interpretation of the data given in the technical documentation.

The most commonly confused parameters are resolution and accuracy, although these two characteristics of a real ADC are extremely weakly related. Resolution is not identical to precision, a 12-bit ADC may have less precision than an 8-bit ADC. For an ADC, resolution is a measure of how many segments the input range of the measured analog signal can be divided into (for example, for an 8-bit ADC, this is 28 = 256 segments). Accuracy characterizes the total deviation of the conversion result from its ideal value for a given input voltage. That is, the resolution characterizes the potential capabilities of the ADC, and the set of accuracy parameters determines the feasibility of such a potential capability.

The ADC converts the input analog signal into an output digital code. For real converters manufactured in the form of integrated circuits, the conversion process is not ideal: it is affected by both the technological spread of parameters during production and various external interference. Therefore, the digital code at the output of the ADC is determined with an error. The specification for the ADC indicates the errors that the converter itself gives. They are usually divided into static and dynamic. At the same time, it is the end application that determines which characteristics of the ADC will be considered decisive, the most important in each specific case.

Static error

In most applications, an ADC is used to measure a slowly varying, low frequency signal (eg from a temperature sensor, pressure sensor, strain gauge, etc.) where the input voltage is proportional to a constant physical quantity. Here the main role is played by the static measurement error. In the ADC specification, this type of error is defined by additive error (Offset), multiplicative error (Full-Scale), differential non-linearity (DNL), integral non-linearity (INL) and quantization error. These five characteristics allow you to fully describe the static error of the ADC.

Ideal Transfer Response of ADC

The transfer characteristic of an ADC is a function of the dependence of the code at the ADC output on the voltage at its input. Such a graph is a piecewise linear function of 2N "steps", where N is the ADC bit depth. Each horizontal segment of this function corresponds to one of the values ​​of the ADC output code (see Fig. 7). If we connect the beginnings of these horizontal segments with lines (at the boundaries of the transition from one code value to another), then the ideal transfer characteristic will be a straight line passing through the origin.

Rice. 7. Ideal transfer characteristic of 3-bit ADC

Rice. 7 illustrates the ideal transfer characteristic for a 3-bit ADC with breakpoints at code transition boundaries. The output code takes on the smallest value (000b) when the input signal is between 0 and 1/8 full scale (the maximum code value of this ADC). Also note that the ADC will reach the full scale code value (111b) at 7/8 of full scale, not at full scale. That. The transition to the maximum value at the output does not occur at full scale voltage, but at a value less than the least significant digit (LSB) than the input full scale voltage. The transfer characteristic can be implemented with a -1/2 LSB offset. This is achieved by shifting the transfer characteristic to the left, which shifts the quantization error from -1...0 LSB to -1/2...+1/2 LSB.

Rice. 8. Transfer characteristic of a 3-bit ADC offset by -1/2LSB

Due to the technological spread of parameters in the manufacture of integrated circuits, real ADCs do not have an ideal transfer characteristic. Deviations from the ideal transfer characteristic determine the static error of the ADC and are given in the technical documentation.

The ideal transfer characteristic of the ADC crosses the origin, and the first code transition occurs when the value of 1 LSB is reached. Additive error (offset error) can be defined as the shift of the entire transfer characteristic to the left or right relative to the input voltage axis, as shown in Fig. 9. Thus, a 1/2 LSB offset is deliberately included in the definition of additive ADC error.

Rice. 9. Additive error (Offset Error)

Multiplicative error

The multiplicative error (full scale error) is the difference between the ideal and actual transfer characteristics at the point of maximum output value under the condition of zero additive error (no offset). This manifests itself as a change in the slope of the transfer function, which is illustrated in Fig. ten.

Rice. 10. Multiplicative error (Full-Scale Error)

For an ideal ADC transfer characteristic, the width of each "step" should be the same. The difference in the length of the horizontal segments of this piecewise linear function of 2N "steps" is a differential non-linearity (DNL).

The value of the least significant bit of the ADC is Vref/2N, where Vref is the reference voltage, N is the resolution of the ADC. The voltage difference between each code transition must be equal to the value of LSB. The deviation of this difference from LSB is defined as differential non-linearity. In the figure, this is shown as unequal gaps between "steps" of the code, or as "blurring" of transition boundaries on the ADC transfer characteristic.

Rice. 11. Differential non-linearity (DNL)

Integral non-linearity

Integral non-linearity (INL) is an error that is caused by the deviation of the linear function of the ADC transfer characteristic from a straight line, as shown in Fig. 12. Typically, a transfer function with an integral non-linearity is approximated by a straight line using the least squares method. Often the fitting straight line simply connects the smallest and largest values. The integral nonlinearity is determined by comparing the voltages at which code transitions occur. For an ideal ADC, these transitions will occur at input voltages that are exactly multiples of LSB. And for a real converter, such a condition can be met with an error. The difference between the "ideal" voltage levels at which the code transition occurs and their real values ​​is expressed in LSB units and is called the integral nonlinearity.

Rice. 12. Integral non-linearity (INL)

Quantization error

One of the most significant error components in ADC measurements, quantization error, is the result of the conversion process itself. Quantization error is the error caused by the value of the quantization step and is defined as? least significant digit (LSB) value. It cannot be excluded in analog-to-digital conversions, since it is an integral part of the conversion process, it is determined by the resolution of the ADC and does not change from ADC to ADC with equal resolution.

Dynamic characteristics

The dynamic characteristics of an ADC are usually determined using spectral analysis, from the results of performing a fast Fourier transform (FFT) on an array of ADC output values ​​corresponding to some test input signal.

On fig. 13 shows an example of the frequency spectrum of the measured signal. The zero harmonic corresponds to the fundamental frequency of the input signal. Everything else is noise, which includes harmonic distortion, thermal noise, 1/f noise, and quantization noise. Some noise components are generated by the ADC itself, some may be input to the ADC from external circuits. Harmonic distortion, for example, can be contained in the measured signal and simultaneously generated by the ADC during the conversion process.

Rice. 13. The result of the FFT execution on the output data of the ADC

Signal-to-noise ratio

The signal-to-noise ratio (SNR) is the ratio of the RMS value of the input signal to the RMS value of the noise (excluding harmonic distortion), expressed in decibels:

SNR(dB) = 20 log [ Vsignal(rms)/ Vnoise(rms) ]

This value allows you to determine the proportion of noise in the measured signal in relation to the useful signal.

Rice. 14. SNR - Signal to Noise Ratio

Rice. 15. FFT Reflects Harmonic Distortion

The noise measured in the SNR calculation does not include harmonic distortion, but does include quantization noise. For an ADC with a certain resolution, it is quantization noise that limits the capabilities of the converter to a theoretically better signal-to-noise ratio, which is defined as:

SNR(db) = 6.02 N + 1.76,

where N is the resolution of the ADC.

The ADC quantization noise spectrum of standard architectures has a uniform frequency distribution. Therefore, the magnitude of this noise cannot be reduced by increasing the conversion time and then averaging the results. Quantization noise can only be reduced by making measurements with a larger ADC.

A feature of the sigma-delta ADC is that its quantization noise spectrum is unevenly distributed over frequency - it is shifted towards high frequencies. Therefore, by increasing the measurement time (and, accordingly, the number of samples of the measured signal), accumulating and then averaging the obtained sample (low-pass filter), one can obtain a measurement result with a higher accuracy. Naturally, in this case, the total conversion time will increase.

Other sources of ADC noise include thermal noise, 1/f noise, and reference jitter.

General harmonic distortion

Non-linearity in the results of data conversion leads to the appearance of harmonic distortion. Such distortions are observed as "emissions" in the frequency spectrum at even and odd harmonics of the measured signal (Fig. 15).

This distortion is defined as total harmonic distortion (THD). They are defined as:

The amount of harmonic distortion decreases at high frequencies to the point where the amplitude of the harmonics becomes less than the noise level. Thus, if we analyze the contribution of harmonic distortion to the conversion results, this can be done either in the entire frequency spectrum, while limiting the amplitude of the harmonics by the noise level, or by limiting the bandwidth for analysis. For example, if our system has a low-pass filter, then we are simply not interested in high frequencies and high-frequency harmonics are not subject to accounting.

Signal-to-noise ratio and distortion

Signal-to-noise and distortion ratio (SiNAD) more fully describes the noise characteristics of an ADC. SiNAD takes into account the amount of both noise and harmonic distortion in relation to the useful signal. SiNAD is calculated using the following formula:

Rice. 16. Dynamic range free from harmonics

The ADC specification, given in the technical documentation for microcircuits, helps to reasonably select a converter for a particular application. As an example, consider the specification of the ADC integrated into the new C8051F064 microcontroller manufactured by Silicon Laboratories.

Microcontroller C8051F064

The C8051F064 crystal is a high-speed 8-bit microcontroller for joint processing of analog and digital signals with two integrated 16-bit successive approximation ADCs. Built-in ADCs can operate in single-wire and differential modes with a maximum performance of up to 1M samples/sec. The table shows the main characteristics of the ADC of the C8051F064 microcontroller. To evaluate the C8051F064's digital and analog processing capabilities on your own, you can use the inexpensive C8051F064EK evaluation kit (Figure 17). The kit includes an evaluation board based on the C8051F064, a USB cable, documentation, and software for testing the analog dynamic and static characteristics of an integrated high-precision 16-bit ADC.

Table. V DD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, V REF = 2.50 V (REFBE=0), -40 to +85° unless otherwise noted

Rice. 17. Evaluation kit C8051F064EK

Literature

1. http://www.wbc-europe.com/en/services/pim_application_guide.html
2. www.silabs.com

Wolfgang Reis (WBC GmbH)

When using a computer to process information from various devices (objects, processes), in which information is represented by continuous (analog) signals, it is required to convert an analog signal into a digital one - into a number proportional to the amplitude of this signal, and vice versa. In general, the analog-to-digital conversion procedure consists of three stages)