This article discusses the main issues related to the principle of operation of ADCs of various types. At the same time, some important theoretical calculations concerning the mathematical description of analog-to-digital conversion remained outside the scope of the article, but links are provided by which the interested reader can find a deeper consideration of the theoretical aspects of the ADC operation. Thus, the article is more concerned with understanding the general principles of ADC operation than with a theoretical analysis of their work.
Introduction
As a starting point, let's define analog-to-digital conversion. Analog-to-digital conversion is the process of converting an input physical quantity into its numerical representation. An analog-to-digital converter is a device that performs this conversion. Formally, the input value of the ADC can be any physical quantity - voltage, current, resistance, capacitance, pulse repetition rate, shaft rotation angle, etc. However, for the sake of definiteness, in what follows, under the ADC, we will mean exclusively voltage-to-code converters.
The concept of analog-to-digital conversion is closely related to the concept of measurement. Measurement refers to the process of comparing the measured value with a certain standard; during analog-to-digital conversion, the input value is compared with a certain reference value (as a rule, with a reference voltage). Thus, analog-to-digital conversion can be viewed as a measurement of the value of an input signal, and all concepts of metrology, such as measurement errors, are applicable to it.
Main characteristics of ADC
The ADC has many characteristics, of which the main ones are the conversion frequency and bit depth. The conversion rate is usually expressed in samples per second (SPS), and the bit depth is in bits. Modern ADCs can be up to 24 bits wide and have a conversion rate up to GSPS units (not simultaneously, of course). The higher the speed and bit depth, the more difficult it is to obtain the required characteristics, the more expensive and more complex the converter. Conversion speed and bit depth are related to each other in a certain way, and we can increase the effective conversion bit depth by sacrificing speed.
ADC types
There are many types of ADCs, however, for the purposes of this article, we will limit ourselves to considering only the following types:
- ADC parallel conversion (direct conversion, flash ADC)
- Successive Approximation ADC (SAR ADC)
- delta sigma ADC (charge balanced ADC)
The ADCs of direct (parallel) conversion have the highest speed and lowest bit depth. For example, the TLC5540 parallel conversion ADC from Texas Instruments has a speed of 40MSPS with a bit width of only 8 bits. ADCs of this type can have conversion rates up to 1 GSPS. It can be noted here that pipelined ADCs have even greater performance, but they are a combination of several ADCs with lower performance and their consideration is beyond the scope of this article.
The middle niche in the bit-rate row is occupied by successive approximation ADCs. Typical values are 12-18 bits at a conversion rate of 100KSPS-1MSPS.
The greatest accuracy is achieved by sigma-delta ADCs with a capacity of up to 24 bits inclusive and a speed from SPS units to KSPS units.
Another type of ADC that has found use in the recent past is the integrating ADC. Integrating ADCs are now largely superseded by other types of ADCs, but may be found in older instrumentation.
ADC direct conversion
Direct-conversion ADCs became widespread in the 1960s and 1970s, and were introduced into integrated circuits in the 1980s. They are often used as part of "pipelined" ADCs (they are not considered in this article), and have a capacity of 6-8 bits at speeds up to 1 GSPS.
The architecture of a direct-conversion ADC is shown in Fig. one
Rice. 1. Block diagram of direct conversion ADC
The principle of operation of the ADC is extremely simple: the input signal is fed simultaneously to all the "plus" inputs of the comparators, and a number of voltages are fed to the "minus" ones, obtained from the reference voltage by dividing by resistors R. For the circuit in Fig. 1 this row will be like this: (1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16) Uref, where Uref is the ADC reference voltage.
Let the voltage equal to 1/2 Uref be applied to the ADC input. Then the first 4 comparators will work (if you count from the bottom), and logical units will appear at their outputs. The priority encoder will form a binary code from the "column" of ones, which is fixed by the output register.
Now the advantages and disadvantages of such a converter become clear. All comparators operate in parallel, the circuit delay time is equal to the delay time in one comparator plus the delay time in the encoder. The comparator and encoder can be made very fast, as a result, the whole circuit has a very high speed.
But to get N bits, 2 ^ N comparators are needed (and the complexity of the encoder also grows as 2 ^ N). The diagram in Fig. 1. contains 8 comparators and has 3 bits, to get 8 bits you need 256 comparators, for 10 bits - 1024 comparators, for a 24-bit ADC over 16 million of them would be needed. However, the technique has not yet reached such heights.
Successive approximation ADC
A Successive Approximation Register (SAR) analog-to-digital converter measures the magnitude of an input signal by performing a series of successive "weightings", that is, comparing the magnitude of the input voltage with a number of values generated as follows:
1. at the first step, a value equal to 1 / 2Uref is set at the output of the built-in digital-to-analog converter (hereinafter we assume that the signal is in the range (0 - Uref).
2. if the signal is greater than this value, then it is compared with the voltage lying in the middle of the remaining interval, i.e., in this case, 3 / 4Uref. If the signal is less than the set level, then the next comparison will be made with less than half of the remaining interval (i.e., with the 1 / 4Uref level).
3. Step 2 is repeated N times. Thus, N comparisons ("weightings") generate N bits of the result.
Rice. 2. Block diagram of the successive approximation ADC.
Thus, the SAR ADC consists of the following units:
1. Comparator. It compares the input value and the current value of the "weight" voltage (in Fig. 2. marked with a triangle).
2. Digital to Analog Converter (DAC). It generates a "weight" voltage value based on the input digital code.
3. Register of successive approximation (Successive Approximation Register, SAR). It implements the successive approximation algorithm, generating the current value of the code supplied to the DAC input. All this ADC architecture is named after it.
4. Sample-hold scheme (Sample / Hold, S / H). For the operation of this ADC, it is fundamentally important that the input voltage remains constant throughout the conversion cycle. However, "real" signals tend to change over time. The sample-and-hold circuit “remembers” the current value of the analog signal, and keeps it unchanged throughout the entire operating cycle of the device.
The advantage of the device is its relatively high conversion speed: the conversion time of an N-bit ADC is N clock cycles. The conversion accuracy is limited by the accuracy of the internal DAC and can be 16-18 bits (now 24-bit SAR ADCs, for example, the AD7766 and AD7767, have begun to appear).
Delta Sigma ADC
Finally, the most interesting type of ADC is the sigma-delta ADC, sometimes referred to in the literature as a charge-balanced ADC. The block diagram of a sigma-delta ADC is shown in Fig. 3.
Fig. 3. Block diagram of a sigma-delta ADC.
The principle of operation of this ADC is somewhat more complex than that of other types of ADC. Its essence is that the input voltage is compared with the voltage value accumulated by the integrator. Pulses of positive or negative polarity are supplied to the integrator input, depending on the comparison result. Thus, this ADC is a simple tracking system: the voltage at the output of the integrator "tracks" the input voltage (Fig. 4). The result of this circuit is a stream of zeros and ones at the output of the comparator, which is then passed through a digital low-pass filter, resulting in an N-bit result. LPF in Fig. 3. Combined with a "decimator", a device that reduces the repetition rate of samples by "decimating" them.
Rice. 4. Sigma-delta ADC as a tracking system
For the sake of the severity of the presentation, it must be said that in Fig. 3 is a block diagram of a first order sigma-delta ADC. A second-order sigma-delta ADC has two integrators and two feedback loops, but will not be covered here. Those interested in this topic can refer to.
In fig. 5 shows the signals in the ADC at a zero level at the input (top) and at the level Vref / 2 (bottom).
Rice. 5. Signals in the ADC at different signal levels at the input.
Now, without delving into complex mathematical analysis, let's try to understand why sigma-delta ADCs have a very low level of intrinsic noise.
Consider the block diagram of the sigma-delta modulator shown in Fig. 3, and represent it in this form (Fig. 6):
Rice. 6. Block diagram of the sigma-delta modulator
Here the comparator is represented as an adder that adds the continuous wanted signal and the quantization noise.
Let the integrator have a transfer function 1 / s. Then, representing the useful signal as X (s), the output of the sigma-delta modulator as Y (s), and the quantization noise as E (s), we obtain the ADC transfer function:
Y (s) = X (s) / (s + 1) + E (s) s / (s + 1)
That is, in fact, the sigma-delta modulator is a low-pass filter (1 / (s + 1)) for the desired signal, and a high-pass filter (s / (s + 1)) for noise, both filters having the same cutoff frequency. The noise concentrated in the high-frequency region of the spectrum is easily removed by the digital low-pass filter, which is located after the modulator.
Rice. 7. The phenomenon of "displacement" of noise in the high-frequency part of the spectrum
However, it should be understood that this is an extremely simplified explanation of the noise shaping phenomenon in a sigma-delta ADC.
So, the main advantage of a sigma-delta ADC is high accuracy due to extremely low intrinsic noise. However, to achieve high accuracy, it is necessary that the cutoff frequency of the digital filter be as low as possible, many times less than the operating frequency of the sigma-delta modulator. Therefore, sigma-delta ADCs have a slow conversion speed.
They can be used in audio engineering, but are mainly used in industrial automation for converting sensor signals, in measuring instruments, and in other applications where high accuracy is required. but no high speed required.
A bit of history
The oldest ADC reference in history is probably the Paul M. Rainey patent, "Facsimile Telegraph System," U.S. Patent 1,608,527, Filed July 20, 1921, Issued November 30, 1926. The device depicted in the patent is actually a 5-bit direct conversion ADC.
Rice. 8. First patent for ADC
Rice. 9. ADC direct conversion (1975)
The device shown in the figure is a MOD-4100 direct conversion ADC from Computer Labs, 1975, assembled on the basis of discrete comparators. There are 16 comparators (they are located in a semicircle, in order to equalize the signal propagation delay to each comparator), therefore, the ADC has a capacity of only 4 bits. Conversion speed 100 MSPS, power consumption 14 watts.
The following figure shows an advanced version of the direct conversion ADC.
Rice. 10. ADC direct conversion (1970)
A 1970 VHS-630, manufactured by Computer Labs, had 64 comparators, had 6 bits, 30MSPS, and consumed 100 watts (the 1975 version of the VHS-675 had 75 MSPS and 130 watts).
Literature
W. Kester. ADC Architectures I: The Flash Converter. Analog Devices, MT-020 Tutorial.
Sometimes one gets the impression that the digital world almost completely merges with the real one. But despite the emergence of such systems as "gigaFLOPS", "22 nm" and many others, the real world stubbornly remains analog and not digital at all, and we still have to work with our digital systems, which are present almost everywhere in the modern world.
D / A Converter The DAC converts an input digital signal to an analog output. Accuracy can vary from manufacturer to manufacturer, but we will describe D / A converters with a resolution of 8 to 16 bits and rates up to 10 MS / s. These digital-to-analog converters DAC are used in various systems - audio and video equipment, processor control, measuring instruments, automation systems, electric drive systems and many others. Each individual system has individual requirements for the DAC, for example, resolution, static and dynamic characteristics, power consumption, and others.
Parameters and datasheet include offset error, differential nonlinearity (DNL), integral nonlinearity (INL), and other parameters necessary to provide good performance in DC systems such as drive control or process control.
Some applications, such as signal generation on a monitor screen, emphasize the need for good performance on AC, which is specified in the datasheet in terms of lag time, noise, and bandwidth. Making the device itself using a DAC is much more difficult than choosing a digital-to-analog converter from the catalog, because in addition to the DAC, the system will include many more electronic components, the influence of which must also be taken into account. Below we will try to consider this.
Content:
Three main architectures for precision DACs
When choosing the accuracy of the D / A converter for your system, it is imperative that the DAC specification meets the system requirements. Compared to the plethora of ADC architectures, the choice of a D / A converter can seem like an easy task since there are only three main architectures in a DAC. But it only seems that the task is easy, because the difference in performance of each of the architectures is quite significant.
The DAC uses three main architectures - string (serial), R-2R, multiplying DAC (MDAC).
String D / A Converter
The concept behind the string D / A converter comes from Lord Kelvin since the mid 1800s:
The input decoder has several switches, one for each bit pattern. Each digital input is connected to the corresponding voltage of the output voltage amplifier.
An N-bit DAC consists of a sequence of 2 N matching resistors, plus a voltage source at one end, and a ground at the other. A three-bit DAC (picture above) requires eight resistors and seven switches, but these numbers grow very strongly with increasing bit depth, and for a 16-bit DAC, 65536 resistors are needed !!! This number is very large, even for modern systems. To reduce the number of resistors, interpolation amplifiers and taps to separate resistors are used.
String or serial digital-to-analogue converters are well suited for most precision applications such as motion control, automatic control systems (in servo drives and in motor control).
The output voltage of string DACs is initially monotonic with good differential nonlinearity (DNL), but its integral nonlinearity (INL) is not very good, since it directly depends on the resistor error. From an AC point of view, String DACs exhibit lower performance than other architectures because they have relatively high noise levels due to the high impedance of the resistors, and the switching structure leads to slower signal processing during transitions, while limiting the update rate.
R-2R architecture
This architecture is the most common among digital-to-analog converters and its circuit is shown below:
This architecture uses only resistors with two different resistances, the ratios between which are defined as 2 to 1.
When a specific bit is set, the corresponding 2R resistor is switched to the V REF - H position, otherwise it is set to the V REF - L (ground) position. The result is an output voltage that will be the sum of all 2R ladder voltages.
The R-2R architecture is well suited for industrial installations and devices. They are more accurate than string DACs, have lower noise due to lower net impedance, and have better INL and DNL performance.
The signal conversion in an R-2R converter is to switch the 2R pin between V REF - H and V REF - L. Internal resistors and switches inside the device do not match perfectly, which can lead to certain failures during the switching process.
Multiplying D / A Converter MDAC
The multiplying converter MDAC also uses the R-2R architecture, but with the reference voltage V REF. The diagram is below:
When the bit is set, the corresponding 2R resistor is connected to virtual ground - the summing op-amp. That is why the multiplying digital-to-analog converter does not provide voltage, but current, while the reference voltage V REF can exceed the nominal voltage or even be negative.
The V REF source sees MDAC as a constant resistance of R, so it always has a constant output current, which improves performance during fast transitions since there is no need to wait for the reference voltage to recover. Depending on the digital code, the current stream is divided into an output pin and a ground pin. This means that the output impedance will be different, and this makes it somewhat difficult to choose an external op-amp.
To improve performance, the MDAC outputs include an internal resistor as feedback with a thermal response that roughly matches the internal step resistor. Internal noise from the multiplying D / A converter comes from both the step resistances and the feedback resistance. Since the output impedance is code-dependent, the noise gain also depends on it, although the noise level of the MDAC is much lower than that of serial (string) DACs. It is worth noting that an external op amp can be low noise.
One of the drawbacks is that the input signal is the opposite of the output, which in turn requires an additional inverting operation.
Understanding AC Performance Parameters
To get the best performance out of an AC D / A converter, there are some subtleties to be understood as well as the possible steps you can take to optimize.
The time required for the op-amp to reach its final value is one of the main indicators of the quality of a DAC. Below are the sections of the response time of the digital-to-analog converter:
- Dead time ( Dead time): this is the time required to reach 10% of the required analog output value, starting from the moment when the digital code entered the digital-to-analog converter;
- Output rise time ( Slew time): time required for the analog output to rise from 10% to 90%;
- Recovery and settling time ( Recovery time, linear settling time): overshoot and establishment of an analog signal of a given shape;
Once the value of the analog output signal is within the acceptable error range, the process is considered complete even if the signal still fluctuates, but does not go beyond the acceptable error range.
The transient response of a real 18-bit, single-channel, R-2R DAC988 DAC is shown below:
The settling time is measured from the moment the LDAC signal goes low, after which a transient process begins in the system. Note that the signal decay process is the longest, with a long recovery process and insignificant influence of the static signal on it.
Switching errors
The ideal change in the output signal of the DAC is a monotonic rise or fall, but in reality this is not the case, and the signal changes occur abruptly. Unlike settling time, switching error is caused by mismatch of internal switching (dominant factor), or by capacitive coupling between digital input and analog output signals:
The error is characterized by the area under the positive and negative false pulses and is measured in volt-seconds (most often in μV ∙ s or nV ∙ s).
As the number of parallel switches increases, so does the error. This is one of the shortcomings of the R-2R architecture. Errors in the R-2R architecture are most noticeable when changing all bits or when switching the most significant bits, when switching from 0x7FFF to 0x8000 (for 16-bit DACs).
If it is impossible to reduce the number of switching series resistors, then they are used at the output of the converter, the circuits are shown below:
Figure a) shows the simplest RC filter, which is installed at the output and allows you to slightly reduce the amplitude of the output error, however, thereby it delays the slew rate of the signal, which increases the lag time. Figure b) shows an addition sampling and chain hold option. Yes, this allows you to reduce the error to almost zero, but it is extremely difficult to implement such a scheme, since it imposes strict requirements on the response time, as well as tight synchronization with the DAC refresh rate.
Sources of noise
Noise is one of the most important performance components of a modern AC D / A converter. There are three main sources of noise - internal resistor circuits, internal and external amplifiers, and voltage references. The effect of internal resistors on converter noise was discussed earlier in this article, so let's look at the other two noise sources.
Noise of an external op-amp
The DAC amplifier output is another source of noise. MDAC uses an external op-amp, but other architectures use an internal op-amp, which affects the overall output noise figure.
Noise in an op-amp circuit has three main components:
- 1 / f noise or flicker noise;
- Broadband voltage noise or white noise;
- Noise voltages and currents across resistors;
The first two are considered intrinsic properties of the op-amp itself, and the bandwidth is limited by the DAC itself, which greatly reduces the effect of wideband noise. For best AC performance, consider op amps with low 1 / f noise.
Noise from external reference voltage V REF
The DAC output noise is directly related to the noise in the reference voltage, which can be either external or internal. For maximum performance and minimum noise, use quality voltage references. There is a huge selection of voltage references from several manufacturers.
Conclusion
Getting the most AC performance from a precision DAC is a combination of understanding the specifications, choosing the right architecture and adding the right external components, and of course following proven techniques for selecting and sizing electronic components.
Digital-to-analog converters (DAC) - designed to convert digital signals to analog. Such a conversion is necessary, for example, when restoring an analog signal, previously converted to digital for transmission over a long distance or storage (such a signal, in particular, can be sound). Another example of using such a conversion is obtaining a control signal for digital control of devices, the operating mode of which is determined directly by an analog signal (which, in particular, occurs when controlling motors).
(xtypo_quote) The main parameters of the DAC include resolution, settling time, nonlinearity error, etc. (/ xtypo_quote)
Resolution is the reciprocal of the maximum number of steps for quantizing the analog output signal. Settling time t set - the time interval from the application of the code to the input until the moment when the output signal enters the specified limits, determined by the error. Nonlinearity error is the maximum deviation of the graph of the dependence of the output voltage on the voltage specified by a digital signal with respect to the ideal straight line in the entire conversion range.
Like the ones under consideration, DACs are the "link" between analog and digital electronics. There are various principles for constructing an ADC.
DAC circuit with summation of weight currents
In fig. 3.88 shows the DAC circuit with the summation of the weight currents.
Key S 5 is closed only when all keys S 1 ... S 4 are open (with u out = 0). U 0
- reference voltage. Each resistor in the input circuit corresponds to a specific bit of the binary number.
This DAC is essentially an op-amp-based inverting amplifier. The analysis of such a scheme is not difficult. So, if one key is closed
S1, then u out = −U 0 R oc / R
which corresponds to the first and zeros in the remaining digits.
From the analysis of the circuit, it follows that the output voltage module is proportional to the number, the binary code of which is determined by the state of the keys S 1 ... S 4. The currents of the keys S 1 ... S 4 are summed up at the point "a", and the currents of different keys are different (have different "weight"). This determines the name of the circuit.
From the above it follows that u out = - (U 0 R oc / R) S 1 - (U 0 R oc / (R / 2)) S 2 - - (U 0 R oc / (R / 4)) S 3 - (U 0 R oc / (R / 8)) S 4 = = - (U 0 R oc / R) (8S 4 + 4S 3 + 2S 2 + S 1)
where S i, i = 1, 2, 3, 4 takes on the value 1 if the corresponding key is closed, and 0 if the key is open.
The state of the keys is determined by the input transformed code. The circuit is simple, but it has disadvantages: significant changes in the voltage across the keys and the use of resistors with very different resistances. It is difficult to provide the required accuracy of these resistances.
DAC based on resistive matrix R - 2R
Consider a DAC based on a resistive matrix R - 2R (constant resistance matrix) (Fig. 3.89). 
The circuit uses the so-called changeover keys S 1 ... S 4, each of which in one of the states is connected to a common point, so the voltages on the keys are low. Key S 5 is closed only when all keys S 1 ... S 4 are connected to a common point. The input circuit uses resistors with only two different resistance values.
From the analysis of the circuit, you can see that for it, the output voltage module is proportional to the number, the binary code of which is determined by the state of the keys S 1 ... S 4. The analysis is easy to carry out considering the following. Let each of the keys S 1 ... S 4 be connected to a common point. Then, as it is easy to see, the voltage relative to the common point at each next of the points "a" ... "d" is 2 times greater than in the previous one. For example, the voltage at point "b" is 2 times greater than at point "a" (the voltages U a, U b, U c and U d at these points are determined as follows:
Let's assume that the state of the specified keys has changed. Then the voltages at points "a" ... "d" will not change, since the voltage between the inputs of the operational amplifier is practically zero.
From the above it follows that:
u out = - (U 0 R oc / 2R) S 4 - ((U 0/2) R oc / 2R) S 3 - ((U 0/4) R oc / 2R) S 2 - (( U 0/8) R oc / 2R) S 1 = - (U 0 R oc / 16R) (8S 4 + 4S 3 + 2S 2 + S 1)
where S i, i = 1, 2, 3, 4 takes on the value 1 if the corresponding key is closed, and 0 if the key is open.
DAC for BCD conversion
Consider a digital-to-analog converter (BCD) conversion (Figure 3.90).
A separate matrix R - 2R (indicated by rectangles) is used to represent each digit of the decimal number. Z 0 ... Z 3 denote the numbers determined by the state of the keys of each matrix R - 2R. The principle of operation becomes clear if we take into account that the resistance of each matrix R, and if we analyze the fragment of the circuit shown in Fig. 3.91. 
It follows from the analysis that
U 2 = U 1 · [(R || 9R) / (8,1R + R || 9R)]
R || 9R = (R 9R) / (R + 9R) = 0.9R
Therefore, U 2 = 0.1 U 1. With this in mind, we get
u out = - (U 0 R oc / 16R) 10 −3 (10 3 Z 3 + 10 2 Z 2 + 10 Z 1 + Z 0)
The most common are DACs of 572, 594, 1108, 1118 and others. 3.2 are given ...
Parameters of some DACs
Analog to digital converter(ADC, English Analog-to-digital converter, ADC) - a device that converts an input analog signal into a discrete code (digital signal). The reverse conversion is carried out using a DAC (digital to analogue converter, DAC).
Typically, an ADC is an electronic device that converts voltage into a binary digital code. However, some non-electronic devices with a digital output should also be classified as ADCs, such as some types of angle-to-code converters. The simplest one-bit binary ADC is a comparator.
Permission
ADC resolution - the minimum change in the value of an analog signal that can be converted by a given ADC - is related to its capacity. In the case of a single measurement without taking into account noise, the resolution is directly determined by the ADC capacity.
The ADC capacity characterizes the number of discrete values that the converter can output at the output. In binary ADCs it is measured in bits, in ternary ADCs it is measured in trites. For example, a binary 8-bit ADC is capable of producing 256 discrete values (0 ... 255), since a ternary 8-bit ADC is capable of producing 6561 discrete values, since.
The voltage resolution is equal to the voltage difference corresponding to the maximum and minimum output code divided by the number of discrete output values. For instance:
Input range = 0 to 10 volts
Binary ADC 12 bits: 212 = 4096 quantization levels
Binary ADC voltage resolution: (10-0) / 4096 = 0.00244 volts = 2.44 mV
Bit depth of ternary ADC 12 trit: 312 = 531 441 quantization level
Voltage resolution of ternary ADC: (10-0) / 531441 = 0.0188 mV = 18.8 μV
Input range = -10 to +10 volts
Bit ADC 14 bits: 214 = 16384 quantization levels
Binary ADC voltage resolution: (10 - (- 10)) / 16384 = 20/16384 = 0.00122 volts = 1.22 mV
Bit depth of ternary ADC 14 trit: 314 = 4 782 969 quantization levels
Voltage resolution of ternary ADC: (10 - (- 10)) / 4782969 = 0.00418 mV = 4.18 μV
In practice, the resolution of the ADC is limited by the signal-to-noise ratio of the input signal. With a high noise intensity at the ADC input, it becomes impossible to distinguish adjacent levels of the input signal, that is, the resolution deteriorates. In this case, the actually achievable resolution is described by the effective number of bits (ENOB), which is less than the actual bit depth of the ADC. When converting a highly noisy signal, the least significant bits of the output code are practically useless, since they contain noise. To achieve the declared bit width, the S / N ratio of the input signal should be approximately 6 dB for each bit of bit depth (6 dB corresponds to a fourfold change in the signal level).
Conversion types
According to the method used by the algorithms, the ADC is divided into:
Consecutive forward enumeration
Successive approximation
Serial sigma-delta modulation
Parallel single stage
Parallel two- or more stage (conveyor)
The transfer characteristic of the ADC is the dependence of the numerical equivalent of the output binary code on the value of the input analog signal. They talk about linear and non-linear ADCs. This division is conditional. Both transmission characteristics are stepped. But for "linear" ADCs it is always possible to draw such a straight line so that all points of the transfer characteristic corresponding to the input values delta * 2 ^ k (where delta is the sampling step, k lies in the range 0..N, where N is the ADC bit width) equidistant from it.
Accuracy
There are several sources of ADC error. Quantization errors and (assuming the ADC should be linear) nonlinearities are inherent in any A / D conversion. In addition, there are so-called aperture errors which are a consequence of the jitter of the clock generator; they appear when the signal is converted as a whole (and not just one sample).
These errors are measured in units called LSB - least significant bit. In the above example of an 8-bit binary ADC, an error in 1 LSB is 1/256 of the full signal range, that is, 0.4%, in a 5-bit ternary ADC, an error in 1 LSB is 1/243 of the full signal range, that is 0.412%, in an 8-bit ternary ADC the error in 1 LSM is 1/6561, that is, 0.015%.
ADC types
The following are the main ways to build electronic ADCs:
ADC direct conversion:
Parallel direct-conversion ADCs, completely parallel to the ADCs, contain one comparator for each discrete input level. At any time, only comparators corresponding to levels below the input signal level output an excess signal at their output. Signals from all comparators go either directly to a parallel register, then the code is processed in software, or to a hardware logical encoder that generates the required digital code in hardware, depending on the code at the encoder input. The data from the encoder is recorded in a parallel register. The sampling rate of parallel ADCs generally depends on the hardware characteristics of the analog and logic gates, as well as the required sampling rate.
Parallel direct-conversion ADCs are the fastest, but usually have a resolution of no more than 8 bits, since they entail high hardware costs (comparators). ADCs of this type have a very large chip size, high input capacitance, and can produce short-term output errors. Often used for video or other high frequency signals, and are widely used in industry to monitor rapidly changing processes in real time.
Pipelined ADC operation is used in parallel-to-serial direct-conversion ADCs, in contrast to the normal operation of parallel-serial direct-conversion ADCs, in which data is transmitted after complete conversion, during pipeline operation, partial conversion data is transmitted as soon as it is ready until the complete conversion is completed.
A successive approximation ADC, or bit-balanced ADC, contains a comparator, an auxiliary DAC, and a successive approximation register. The ADC converts an analog signal to a digital one in N steps, where N is the ADC capacity. At each step, one bit of the desired digital value is determined, starting from the NWR and ending with the MWR. The sequence of actions for determining the next bit is as follows. The auxiliary DAC is set to an analog value formed from the bits already defined in the previous steps; the bit to be determined in this step is set to 1, the least significant bits are set to 0. The value obtained on the auxiliary DAC is compared with the input analog value. If the value of the input signal is greater than the value on the auxiliary DAC, then the determined bit is set to 1, otherwise 0. Thus, the determination of the final digital value is like a binary search. ADCs of this type have both high speed and good resolution. However, in the absence of a sample storage device, the error will be much larger (imagine that after digitizing the largest bit, the signal begins to change).
ADCs of differential coding (English delta-encoded ADC) contain a reversing counter, the code from which goes to the auxiliary DAC. The input signal and the signal from the auxiliary DAC are compared on a comparator. Due to negative feedback from the comparator to the counter, the code on the counter is constantly changing so that the signal from the auxiliary DAC differs as little as possible from the input signal. After some time, the difference between the signals becomes less than the LSM, while the counter code is read as the digital output signal of the ADC. ADCs of this type have a very large input signal range and high resolution, but the conversion time depends on the input signal, although it is limited from the top. In the worst case, the conversion time is equal to Tmax = (2q) / fс, where q is the ADC capacity, fс is the counter clock generator frequency. Differential-encoding ADCs are usually a good choice for digitizing real-world signals, since most signals in physical systems are not prone to hopping. Some ADCs use a combined approach: differential coding and successive approximation; this works especially well in cases where the high frequency components in the signal are known to be relatively small.
Ramp comparison ADCs (some ADCs of this type are called Integrating ADCs, also include sequential ADCs) contain a sawtooth voltage generator (in a sequential ADC, a step voltage generator consisting of a counter and a DAC), a comparator and a time counter. The sawtooth waveform rises linearly from low to high, then quickly falls off to low. At the start of the rise, the time counter starts. When the sawtooth signal reaches the input level, the comparator is triggered and stops the counter; the value is read from the counter and fed to the ADC output. This type of ADC is the simplest in structure and contains the minimum number of elements. At the same time, the simplest ADCs of this type have rather low accuracy and are sensitive to temperature and other external parameters. The sawtooth generator can be built around a counter and an auxiliary DAC to increase accuracy, but this structure has no other advantages over successive approximation and differential encoding ADCs.
ADCs with charge balancing (these include ADCs with two-stage integration, ADCs with multi-stage integration, and some others) contain a constant current generator, a comparator, a current integrator, a clock generator, and a pulse counter. The transformation takes place in two stages (two-stage integration). In the first step, the input voltage value is converted into a current (proportional to the input voltage), which is fed to the current integrator, the charge of which is initially zero. This process lasts for TN time, where T is the period of the clock generator, N is a constant (a large integer, determines the charge accumulation time). After this time, the integrator input is disconnected from the ADC input and connected to the constant current generator. The polarity of the generator is such that it reduces the charge stored in the integrator. The discharge process lasts until the charge in the integrator decreases to zero. Discharge time is measured by counting clock pulses from the moment the discharge starts until zero charge is reached on the integrator. The counted number of clock pulses will be the output code of the ADC. It can be shown that the number of pulses n, counted during the discharge time, is equal to: n = Uin N (RI0) −1, where Uin is the input voltage of the ADC, N is the number of pulses in the accumulation stage (defined above), R is the resistance of the resistor that converts the input voltage into current, I0 is the value of the current from the stable current generator, which discharges the integrator at the second stage. Thus, potentially unstable parameters of the system (first of all, the capacitance of the integrator's capacitor) are not included in the final expression. This is a consequence of the two-stage process: the errors introduced in the first and second stages are mutually subtracted. Even the long-term stability of the clock generator and the comparator bias voltage are not imposed: these parameters must be stable only for a short time, that is, during each conversion (no more than 2TN). In fact, the principle of two-stage integration allows you to directly convert the ratio of two analog quantities (input and reference current) to the ratio of numeric codes (n and N in terms defined above) with little or no additional error. Typical ADCs of this type are 10 to 18 bits wide. An additional advantage is the ability to build converters that are insensitive to periodic interference (for example, interference from the mains supply) due to accurate integration of the input signal over a fixed time interval. The disadvantage of this type of ADC is its low conversion speed. Charge-balanced ADCs are used in high-precision measuring instruments.
ADC with intermediate conversion to pulse repetition rate. The signal from the sensor passes through a level converter and then through a voltage-to-frequency converter. Thus, a signal is sent directly to the input of the logic circuit, the characteristic of which is only the frequency of the pulses. The logical counter accepts these pulses as input during the sampling time, thus giving out to its end a code combination, numerically equal to the number of pulses that arrived at the converter during the sampling time. Such ADCs are quite slow and not very accurate, but nevertheless they are very simple to implement and therefore have a low cost.
Sigma-delta-ADC (also called delta-sigma ADC) performs analog-to-digital conversion with a sampling rate many times higher than the required one and, by filtering, leaves only the required spectral band in the signal.
Non-electronic ADCs are usually built on the same principles.
Commercial ADCs
As a rule, they are produced in the form of microcircuits.
For most ADCs, the bit width is from 6 to 24 bits, the sampling rate is up to 1 MHz. Mega and gigahertz ADCs are also available (February 2002). Megahertz ADCs are required in digital video cameras, video capture devices, and digital TV tuners to digitize the composite video signal. Commercial ADCs typically have an output error of ± 0.5 to ± 1.5 LSB.
One of the factors that add to the cost of ICs is the number of pins, since they force the package to be made larger and each pin must be connected to a die. To reduce the number of pins, often ADCs operating at low sample rates have a serial interface. Serial ADCs are often used to increase wiring density and create a smaller board.
Often ADC microcircuits have several analog inputs connected inside the microcircuit to a single ADC through an analog multiplexer. Various ADC models may include sample-hold devices, instrumentation amplifiers or high-voltage differential input, and other similar circuits.
Other applications
Analog-to-digital conversion is used wherever it is required to receive an analog signal and process it digitally.
Special video ADCs are used in computer TV tuners, video input cards, and video cameras to digitize the video signal. Microphone and line audio inputs of computers are connected to audio-ADC.
ADCs are an integral part of data acquisition systems.
8-12 bit successive approximation ADC and 16-24 bit sigma-delta ADC are built into single-chip microcontrollers.
Very fast ADCs are needed in digital oscilloscopes (parallel and pipelined ADCs are used)
Modern balances use ADCs up to 24 bits, which convert the signal directly from a strain gauge sensor (sigma-delta-ADC).
ADCs are part of radio modems and other radio data transmission devices, where they are used in conjunction with a DSP processor as a demodulator.
Ultrafast ADCs are used in base station antenna systems (so-called SMART antennas) and in radar antenna arrays.
Digital-to-analog converter (DAC) - a device for converting a digital (usually binary) code into an analog signal (current, voltage or charge). D / A converters are the interface between the discrete digital world and analog signals.
An analog-to-digital converter (ADC) performs the opposite operation.
An audio DAC usually receives a digital signal at its input in pulse-code modulation (PCM, pulse-code modulation). The task of converting various compressed formats to PCM is handled by the appropriate codecs.
Application
The DAC is always used when it is necessary to convert a signal from digital to analog, for example, in CD players (Audio CD).
DAC types
The most common types of electronic DACs are:
A pulse width modulator is the simplest type of DAC. A stable current or voltage source is periodically switched on for a time proportional to the converted digital code, then the resulting pulse sequence is filtered by an analog low-pass filter. This method is often used to control the speed of electric motors, and is also becoming popular in Hi-Fi audio equipment;
Oversampling DACs, such as sigma-delta DACs, are based on variable pulse density. Oversampling allows using a DAC with a lower bit depth to achieve a higher bit depth of the final conversion; often delta-sigma DACs are based on the simplest 1-bit DAC that is nearly linear. A low-bit DAC receives a pulse signal with a modulated pulse density (with a constant pulse width, but with a variable duty cycle), created using negative feedback. Negative feedback acts as a high-pass filter for quantization noise.
Most high-capacity DACs (over 16 bits) are built on this principle due to its high linearity and low cost. Delta-sigma DAC performance reaches hundreds of thousands of samples per second, bit depth - up to 24 bits. A simple first-order or higher-order delta-sigma modulator such as MASH (Multi stage noise SHaping) can be used to generate a pulse density modulated signal. As the oversampling rate increases, the requirements for the output low-pass filter are softened and the suppression of quantization noise improves;
A weighing type DAC, in which each bit of the converted binary code corresponds to a resistor or current source connected to a common summation point. The source current (resistor conductance) is proportional to the weight of the bit to which it corresponds. Thus, all non-zero bits of the code are added to the weight. The weighting method is one of the fastest, but it is characterized by low accuracy due to the need for a set of many different precision sources or resistors and variable impedance. For this reason, weighting DACs are no more than eight bits wide;
Ladder DAC (R-2R chain circuit). In the R-2R-DAC, the values are created in a special circuit consisting of resistors with resistances R and 2R, called a constant impedance matrix, which has two types of switching: direct - a matrix of currents and inverse - a matrix of voltages. The use of the same resistors can significantly improve the accuracy compared to a conventional weighing DAC, since it is relatively easy to manufacture a set of precision elements with the same parameters. DACs of the R-2R type allow to push back the restrictions on the bit width. With laser trimmed resistors on a single substrate, an accuracy of 20-22 bits is achieved. Most of the conversion time is spent in the operational amplifier, so it should have maximum performance. DAC speed of a few microseconds or less (i.e. nanoseconds);
SpecificationsDACs are located at the beginning of the analog path of any system, therefore the DAC parameters largely determine the parameters of the entire system as a whole. The following are the most important characteristics of a DAC.
Bit depth is the number of different output signal levels that the DAC can reproduce. Usually given in bits; the number of bits is the base 2 logarithm of the number of levels. For example, a one-bit DAC is capable of reproducing two () levels, and an eight-bit DAC is capable of playing 256 () levels. The bit depth is closely related to the effective bit depth (ENOB, Effective Number of Bits), which shows the real resolution attainable on a given DAC.
The maximum sampling rate is the maximum frequency at which the DAC can operate to produce the correct output. In accordance with the Nyquist - Shannon theorem (also known as the Kotelnikov theorem), for the correct reproduction of an analog signal from a digital form, it is necessary that the sampling frequency be at least twice the maximum frequency in the signal spectrum. For example, to reproduce the entire human-audible audio frequency range, the spectrum of which extends up to 20 kHz, it is necessary that the audio signal be sampled with a frequency of at least 40 kHz. The Audio CD standard sets the audio sampling rate to 44.1 kHz; to reproduce this signal, you need a DAC capable of operating at this frequency. In cheap computer sound cards, the sampling rate is 48 kHz. Signals sampled at other frequencies are oversampled up to 48 kHz, which partially degrades the signal quality.
Monotony is the property of a DAC to increase the analog output signal as the input code increases.
THD + N (Total Harmonic Distortion + Noise) is a measure of the distortion and noise introduced into the signal by the DAC. Expressed as a percentage of harmonic power and noise in the output signal. An important parameter for small-signal DAC applications.
Dynamic range is the ratio of the largest to the smallest signal that the DAC can reproduce, expressed in decibels. This parameter is related to bit width and noise threshold.
Static characteristics:
DNL (differential nonlinearity) - characterizes how the increment of the analog signal, obtained when the code is increased by 1 least significant bit (LSB), differs from the correct value;
INL (integral non-linearity) - characterizes how much the transfer characteristic of the DAC differs from the ideal. The ideal characteristic is strictly linear; INL shows how much the voltage at the DAC output for a given code is from the linear characteristic; expressed in minimum wage;
gain;
bias.
Frequency characteristics:
SNDR (signal-to-noise ratio + distortion) - characterizes in decibels the ratio of the output signal power to the total power of noise and harmonic distortion;
HDi (coefficient of the i-th harmonic) - characterizes the ratio of the i-th harmonic to the fundamental harmonic;
THD (Total Harmonic Distortion) - the ratio of the total power of all harmonics (except the first) to the power of the first harmonic
A digital-to-analog converter (DAC) is a device for converting a digital code into an analog signal in proportion to the value of the code.
DACs are used to connect digital control systems with devices that are controlled by the level of an analog signal. Also, DAC is an integral part in many structures of analog-to-digital devices and converters.
The DAC is characterized by a conversion function. It associates a change in a digital code with a change in voltage or current. The DAC conversion function is expressed as follows
U out- the value of the output voltage corresponding to the digital code N in supplied to the DAC inputs.
U max- the maximum output voltage corresponding to the application of the maximum code to the inputs N max
The value To dac, defined by the ratio, is called the digital-to-analog conversion coefficient. Despite the stepped form of the characteristic associated with a discrete change in the input value (digital code), it is believed that DACs are linear converters.
If the value N in represent through the values of the weights of its digits, the transformation function can be expressed as follows
, where
i- bit number of the input code N in; A i- meaning i-th digit (zero or one); U i - weight i-th category; n is the number of bits of the input code (the number of DAC bits).
The discharge weight is determined for a specific bit depth, and is calculated using the following formula
U OP - DAC reference voltage
The principle of operation of most DACs is the summation of the fraction of analog signals (bit weight), depending on the input code.
The DAC can be implemented by summing currents, summing voltages, and dividing voltages. In the first and second cases, in accordance with the values of the bits of the input code, the signals of the generators of currents and sources of EMF are summed up. The latter is a code controlled voltage divider. The last two methods are not widely used due to the practical difficulties of their implementation.
Methods for implementing a DAC with weighted summation of currents
Consider the construction of the simplest DAC with weighted summation of currents.
This DAC consists of a set of resistors and a set of switches. The number of keys and the number of resistors is equal to the number of bits n input code. The resistor values are selected in accordance with the binary law. If R = 3 ohms, then 2R = 6 ohms, 4R = 12 ohms, and so on, i.e. each subsequent resistor is 2 times larger than the previous one. When a voltage source is connected and the keys are closed, a current will flow through each resistor. The values of the currents across the resistors, due to the appropriate choice of their ratings, will also be distributed according to the binary law. When submitting the input code N in the keys are switched on in accordance with the value of the corresponding bits of the input code. The key is closed if the corresponding digit is equal to one. In this case, currents proportional to the weights of these discharges are summed up in the node, and the value of the current flowing from the node as a whole will be proportional to the value of the input code N in.
The resistance of the matrix resistors is chosen quite large (tens of kΩ). Therefore, for most practical cases, the DAC plays the role of a current source for the load. If it is necessary to obtain a voltage at the output of the converter, then a current-voltage converter is installed at the output of such a DAC, for example, on an operational amplifier
However, when the code is changed at the DAC inputs, the amount of current drawn from the reference voltage source changes. This is the main disadvantage of this method of building a DAC. . This construction method can only be used if the voltage reference will be with a low internal resistance. In another case, at the moment of changing the input code, the current taken from the source changes, which leads to a change in the voltage drop across its internal resistance and, in turn, to an additional change in the output current not directly related to the change of the code. This drawback can be eliminated by the structure of the DAC with switching keys.
This structure has two output nodes. Depending on the value of the bits of the input code, the keys corresponding to them are connected to the node associated with the output of the device, or to another node, which is most often grounded. In this case, through each resistor of the matrix, the current flows constantly, regardless of the position of the key, and the amount of current consumed from the reference voltage source is constant.
A common disadvantage of both structures considered is the large ratio between the smallest and largest values of the matrix resistors. At the same time, despite the large difference in resistor ratings, it is necessary to ensure the same absolute accuracy of fitting both the largest and the smallest resistor. In the integrated version of the DAC with the number of digits more than 10, it is rather difficult to provide it.
Structures based on resistive R-2R matrices
With this construction of the resistive matrix, the current in each subsequent parallel branch is two times less than in the previous one. The presence of only two resistors in the matrix makes it quite easy to adjust their values.
The output current for each of the presented structures is proportional simultaneously not only to the value of the input code, but also to the value of the reference voltage. It is often said to be proportional to the product of the two. Therefore, such DACs are called multiplying. Such properties will be possessed by all DAC, in which the formation of the weighted values of the currents corresponding to the weights of the discharges is carried out using resistive matrices.
In addition to their intended use, multiplying DACs are used as analog-to-digital multipliers, as code-controlled resistances and conductivities. They are widely used as building blocks for code-controlled (tunable) amplifiers, filters, reference voltage sources, signal conditioners, etc.
Basic parameters and errors of the DAC
The main parameters that can be seen in the reference:
1. Number of bits - the number of bits of the input code.
2. Conversion factor is the ratio of the output signal increment to the input signal increment for a linear conversion function.
3. The settling time of the output voltage or current is the time interval from the moment of a given code change at the DAC input to the moment at which the output voltage or current will finally enter the zone with the width of the least significant bit ( MHR).
4. Maximum conversion frequency - the highest code change frequency at which the specified parameters correspond to the established standards.
There are other parameters that characterize the performance of the DAC and the features of its functioning. Among them: input voltage of low and high level, current consumption, range of output voltage or current.
The most important parameters for a DAC are those that determine its accuracy characteristics.
Accuracy characteristics of each DAC , first of all, they are determined by the normalized errors.
Errors are divided into dynamic and static. Static errors are errors that remain after the completion of all transient processes associated with a change in the input code. Dynamic errors are determined by transient processes at the DAC output that arose as a result of a change in the input code.
The main types of DAC static errors are:
The absolute conversion error at the end point of the scale is the deviation of the output voltage (current) value from the nominal value corresponding to the end point of the scale of the conversion function. Measured in units of the least significant bit of conversion.
Output zero offset voltage - DC voltage at the output of the DAC with the input code corresponding to the zero value of the output voltage. Measured in units of the least significant digit. Conversion factor error (scale) - associated with the deviation of the slope of the conversion function from the required one.
DAC nonlinearity is the deviation of the actual conversion function from the specified straight line. It is the worst error with which it is difficult to fight.
In general, nonlinearity errors are divided into two types - integral and differential.
Integral nonlinearity error is the maximum deviation of the real characteristic from the ideal one. In fact, the averaged conversion function is considered. Determine this error as a percentage of the final range of the output quantity.
Differential nonlinearity is associated with inaccuracy in setting the bit weights, i.e. with errors of divider elements, scatter of residual parameters of key elements, current generators, etc.
Methods for identification and correction of DAC errors
It is desirable that the error correction is carried out during the manufacture of the transducers (technological adjustment). However, it is often desirable when using a specific sample. BIS in a particular device. In this case, the correction is carried out by introducing into the structure of the device, in addition to LSI DAC additional elements. Such methods are called structural.
The most difficult process is ensuring linearity, since they are determined by the related parameters of many elements and nodes. Most often, only the zero offset, the coefficient
The accuracy parameters provided by technological methods deteriorate when the converter is exposed to various destabilizing factors, first of all, temperature. It is necessary to remember about the aging factor of the elements.
Zero offset and scale errors are easily corrected at the DAC output. To do this, a constant bias is introduced into the output signal, which compensates for the offset of the transducer characteristic. The required conversion scale is set, either by correcting the gain set at the output of the amplifier converter, or by adjusting the value of the reference voltage, if the DAC is a multiplying one.
Correction methods with test control consist in identifying the DAC errors over the entire set of permissible input influences and adding corrections calculated on the basis of this to the input or output value to compensate for these errors.
With any correction method with control by a test signal, the following actions are provided:
1. Measurement of the characteristics of the DAC on a set of test influences sufficient to identify errors.
2. Identification of errors by calculating their deviations from the measurement results.
3. Calculation of corrective corrections for the converted values or the required corrective actions on the corrected blocks.
4. Correction.
The control can be carried out once before installing the transducer in the device using special laboratory measuring equipment. It can also be carried out using specialized equipment built into the device. In this case, control, as a rule, is carried out periodically, all the time until the converter is directly involved in the operation of the device. Such an organization of control and correction of the transducers can be carried out during its operation as part of a microprocessor-based measuring system.
The main disadvantage of any end-to-end inspection method is the long inspection time along with the heterogeneity and the large volume of equipment used.
The values of the corrections determined in one way or another are stored, as a rule, in digital form. Correction of errors, taking into account these corrections, can be carried out both in analog and digital form.
With digital correction, corrections are added taking into account their sign to the input code of the DAC. As a result, a code is sent to the DAC input, at which the required voltage or current value is formed at its output. The simplest implementation of this correction method consists of an adjustable DAC, at the input of which a digital storage device is installed ( Memory)... The input code plays the role of an address code. V Memory at the corresponding addresses, the values of the codes supplied to the corrected DAC, calculated in advance, taking into account the amendments, are entered.
For analog correction, in addition to the main DAC, one additional DAC is used. The range of its output signal corresponds to the maximum value of the error of the corrected DAC. The input code is simultaneously fed to the inputs of the corrected DAC and to the address inputs Memory amendments. From Memory correction, the correction corresponding to the given value of the input code is selected. The correction code is converted into a signal proportional to it, which is added to the output signal of the corrected DAC. Due to the smallness of the required range of the output signal of the additional DAC in comparison with the range of the output signal of the corrected DAC, the inherent errors of the first are neglected.
In some cases, it becomes necessary to correct the dynamics of the DAC operation.
The transient response of the DAC when changing different code combinations will be different, in other words - the settling time of the output signal will be different. Therefore, when using a DAC, the maximum settling time must be considered. However, in some cases it is possible to correct the behavior of the transfer characteristic.
Features of the use of LSI DAC
For the successful application of modern BIS It is not enough for a DAC to know the list of their main characteristics and the basic schemes for their inclusion.
Significant effect on application results BIS The DAC fulfills the operational requirements due to the characteristics of a particular microcircuit. These requirements include not only the use of permissible input signals, power supply voltages, capacitance and load resistance, but also the execution of the sequence of switching on different power supplies, separation of the connection circuits of different power supplies and the common bus, the use of filters, etc.
For precision DACs, the noise output voltage is of particular importance. The peculiarity of the noise problem in the DAC is the presence of voltage surges at its output, caused by switching keys inside the converter. In amplitude, these bursts can reach several tens of weights. MHR and create difficulties in the operation of analog signal processing devices following the DAC. The solution to the problem of suppressing such bursts is to use sample-and-hold devices at the DAC output ( UVH). UVH controlled by the digital part of the system, which forms new code combinations at the DAC input. Before feeding a new code combination UVH is put into storage mode, opening the analog signal transmission circuit to the output. This prevents the DAC output voltage spike from being sent to the pin. UVH, which is then put into tracking mode, repeating the output of the DAC.
Special care when building a DAC based on BIS it is necessary to pay attention to the choice of the operational amplifier, which serves to convert the DAC output current into voltage. When supplying the input code of the DAC at the output OU there will be an error DU due to its bias voltage and equal to
,
where U cm- bias voltage OU; R os- the value of resistance in the feedback circuit OU; R m- the resistance of the resistive matrix of the DAC (output resistance of the DAC), depending on the value of the code applied to its input.
Since the ratio changes from 1 to 0, the error due to U cm, changes in the aisles (1 ... 2) U cm... Influence U cm neglected when using OU, which one .
Due to the large area of transistor switches in CMOS BIS significant output capacitance of the LSI DAC (40 ... 120 pF depending on the value of the input code). This capacitance has a significant effect on the settling time of the output voltage. OU to the required accuracy. To reduce this influence R os shunted by a capacitor With wasps.
In some cases, a bipolar output voltage must be obtained at the DAC output. This can be achieved by introducing an offset of the output voltage range at the output, and for multiplying DACs by switching the polarity of the reference voltage source.
Please note that if you are using an integrated DAC , having the number of bits more than you need, then the inputs of unused bits are connected to the ground bus, unambiguously determining the logic zero level on them. Moreover, in order to work as possible with a large range of the output signal of the LSI DAC for such digits, the digits are taken, starting with the least significant one.
One of the practical examples of DAC applications are signal conditioners of various shapes. Made a small model in the proteus. With the help of a DAC of a controlled MK (Atmega8, although it can be done on Tiny), signals of various shapes are generated. The program is written in C in CVAVR. By pressing the button, the generated signal changes.
LSI DAC DAC0808 National Semiconductor, 8-bit, high-speed, included as per typical diagram. Since its output is current, it is converted into voltage with the help of an inverting amplifier on an op-amp.
In principle, you can even have such interesting figures, does something resemble the truth? If you choose a bit more, you get smoother
Bibliography:
1. Bakhtiyarov G.D., Malinin V.V., Shkolin V.P. Analog-to-digital converters / Ed. GD Bakhtiyarova - M .: Sov. radio. - 1980 .-- 278 p .: ill.
2. Design of analog-digital control microprocessor systems.
3.O.V. Shishov. - Saransk: Publishing house of Mordovs. University 1995. - p.
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