Ministry of Education and Science of Ukraine
Odessa National Maritime Academy
Department of Marine Electronics
on the discipline "Systems of collection and processing of telemetric information"
"Digital-to-analog converters"
Completed:
set FEM and RE
group 3131
Strukov S.M.
Checked: Art. teacher
Kudelkin I.N.
Odessa - 2007
1. Introduction
2. General information
3. Serial DACs
4. Parallel DACs
5. Application of DAC
6. DAC parameters
7. List of used literature
INTRODUCTION
The last decades have been caused by the widespread introduction of microelectronics and computer technology in the national economy, the exchange of information with which is provided by linear analog and digital converters (ADC and DAC).
The modern stage is characterized by large and very large integrated circuits DAC and ADC with high operational parameters: speed, small errors, multi-bit capacity. The inclusion of LSI DAC and ADC in a single, functionally complete unit greatly simplified their implementation in devices and installations used both in scientific research and in industry and made it possible to quickly exchange information between analog and digital devices.
General information
A digital-to-analog converter (DAC) is designed to convert a number, usually defined in the form of a binary code, into a voltage or current proportional to the value of the digital code. The circuitry of digital-to-analog converters is very diverse. In fig. 1 shows the DAC classification scheme according to circuit characteristics. In addition, ICs of digital-to-analog converters are classified according to the following criteria:
o By type of output signal: with current output and voltage output.
o By the type of digital interface: with serial input and with parallel input of the input code.
o By the number of DACs on a chip: single-channel and multichannel.
o By speed: moderate and high speed.
Rice. 1. DAC classification
SERIAL DAC
PWM DAC
Very often, the DAC is part of microprocessor systems. In this case, if high speed is not required, the digital-to-analog conversion can be very easily accomplished using pulse width modulation (PWM). The PWM DAC circuit is shown in Fig. 1a.
Rice. 1. DAC with pulse width modulation
Digital-to-analog conversion is most easily organized if the microcontroller has a built-in pulse-width conversion function (for example, AT90S8515 from Atmel or 87C51GB from Intel). PWM output drives the key S... Depending on the specified conversion bit (for the AT90S8515 controller, 8, 9 and 10-bit modes are possible), the controller, using its timer / counter, generates a sequence of pulses, the relative duration of which is g = t and / T is determined by the ratio
where N- bit conversion, and D- converted code. A low-pass filter smoothes pulses by emphasizing the average voltage value. As a result, the output voltage of the converter
The considered circuit provides almost perfect linearity of conversion, does not contain precision elements (with the exception of the reference voltage source). Its main drawback is low performance.
Switched Capacitor Serial DAC
The above PWM DAC circuit first converts the digital code into a time interval, which is formed using a binary counter quantum by quantum, therefore, to obtain N-bit conversion required 2 N time quanta (ticks). The serial DAC circuit shown in Fig. 2, allows you to perform digital-to-analog conversion in a significantly smaller number of clock cycles.
In this circuit, the capacitances of the capacitors WITH 1 and WITH 2 are equal. Before starting the conversion cycle, the capacitor WITH 2 discharged with a key S 4 . The input binary word is specified as a sequential code. Its conversion is carried out sequentially, starting from the least significant bit d 0. Each transformation bar is made up of two semitracks. In the first half cycle, the capacitor WITH 1 charges to reference voltage U op at d 0 = 1 by key closure S 1 or discharges to zero at d 0 = 0 by key closure S 2. In the second half cycle with open keys S 1 ,S 2 and S 4 the key closes S 3, which causes the charge to split in half between WITH 1 and WITH 2. As a result, we get
U 1 (0)=U out (0) = ( d 0 /2)U op
While on the condenser WITH 2 the charge is conserved, the procedure for charging the capacitor WITH 1 must be repeated for the next discharge d 1 input word. After a new recharge cycle, the voltage across the capacitors will be
Conversion is performed in the same way for the rest of the word digits. As a result, for N-bit DAC output voltage will be equal to
If it is required to save the conversion result for any length of time, a UVC should be connected to the output of the circuit. After the end of the conversion cycle, the sampling cycle should be carried out, the UVC should be put into storage mode and the conversion should be started again.
Thus, the presented circuit performs the transformation of the input code in 2 N quanta, which is significantly less than that of a DAC with PWM. Only two matched small capacitors are required here. The configuration of the analog part of the circuit does not depend on the bit width of the converted code. However, in terms of speed, a serial DAC is significantly inferior to parallel digital-to-analog converters, which limits its scope.
Most parallel DACs are based on the summation of currents, the strength of each of which is proportional to the weight of a digital bit, and only bit currents with values equal to 1 should be summed. Suppose, for example, you want to convert a four-bit binary code into an analog current signal. For the fourth, most significant digit (SZR), the weight will be equal to 2 3 = 8, for the third digit - 2 2 = 4, for the second - 2 1 = 2 and for the least significant (LSD) - 2 0 = 1. If the weight of the MWR I MZR = 1 mA, then I SZR = 8 mA, and the maximum output current of the converter I out max = 15 mA and corresponds to the code 1111 2. It is clear that the code 1001 2, for example, will correspond to I out = 9 mA, etc. Therefore, it is required to build a circuit that provides generation and switching according to the given laws of exact weight currents. The simplest circuit that implements this principle is shown in Fig. 3.
The resistances of the resistors are chosen so that when the keys are closed, a current flows through them corresponding to the weight of the discharge. The key must be closed when the corresponding bit of the input word is equal to one. The output current is determined by the ratio
With a high digit capacity of the DAC, the current setting resistors must be matched with high accuracy. The most stringent accuracy requirements are imposed on high-order resistors, since the spread of currents in them should not exceed the low-order discharge current. Therefore, the spread of resistance in the kth discharge should be less than
It follows from this condition that the spread in the resistance of the resistor, for example, in the fourth digit should not exceed 3%, and in the 10th digit - 0.05%, etc.
The considered scheme, for all its simplicity, has a whole bunch of disadvantages. First, with different input codes, the current consumed from the reference voltage source (RV) will be different, and this will affect the value of the RV output voltage. Secondly, the values of the resistances of the weighting resistors can differ thousands of times, and this makes it very difficult to implement these resistors in semiconductor ICs. In addition, the resistance of high-order resistors in multi-bit DACs can be commensurate with the resistance of a closed switch, and this will lead to a conversion error. Third, in this circuit, a significant voltage is applied to the open switches, which complicates their construction.
These disadvantages are eliminated in the AD7520 DAC circuit (domestic analogue of 572PA1), developed by Analog Devices in 1973, which is now essentially an industrial standard (many serial DAC models are based on it). The indicated scheme is shown in Fig. 4. MOS transistors are used as keys.
Rice. 4. DAC circuit with switches and constant impedance matrix
In this scheme, the setting of the weighting coefficients of the converter steps is carried out by sequentially dividing the reference voltage using a constant impedance resistive matrix. The main element of such a matrix is a voltage divider (Fig. 5), which must satisfy the following condition: if it is loaded on a resistance R n, then its input resistance R input must also take the value R n. The attenuation coefficient of the chain a = U 2 / U 1 at this load must have a given value. When these conditions are met, we obtain the following expressions for the resistances:
With binary coding, a = 0.5. If we put R n = 2R, then R s = R and R p = 2R in accordance with Fig. 4.
Since in any position of the switches S k they connect the lower terminals of the resistors to the common bus of the circuit, the reference voltage source is loaded on a constant input resistance R in = R. This ensures that the reference voltage remains constant for any DAC input code.
According to fig. 4, the output currents of the circuit are determined by the ratios
and the input current
Since the lower terminals of the resistors 2R of the matrix for any state of the switches S k are connected to the common bus of the circuit through a low resistance of the closed keys, the voltages across the keys are always small, within a few millivolts. This simplifies the construction of switches and control circuits and allows the use of a reference voltage from a wide range, including those of different polarity. Since the DAC output current depends on U op linearly (see (8)), converters of this type can be used to multiply an analog signal (feeding it to the reference voltage input) by a digital code. Such DACs are called multiplying DACs (MDAC).
The accuracy of this circuit is reduced by the fact that for DACs with a high bit capacity, it is necessary to match the resistances R 0 of the switches with the discharge currents. This is especially important for high-order keys. For example, in the 10-bit AD7520 DAC, the key MOSFETs of the six most significant bits are made different in area and their resistance R 0 increases according to the binary code (20, 40, 80,:, 640 Ohm). In this way, the voltage drops across the keys of the first six digits are equalized (up to 10 mV), which ensures the monotony and linearity of the DAC transient response. 12-bit DAC 572PA2 has differential nonlinearity up to 0.025% (1 LSB).
DACs on MOS keys have a relatively low speed due to the large input capacity of MOS keys. The same 572PA2 has a settling time of the output current when changing the input code from 000 ... 0 to 111 ... 1, equal to 15 μs. The 12-bit Burr-Braun DAC7611 has an output settling time of 10 µs. At the same time, DACs based on MOS switches have minimal power consumption. The same DAC7611 consumes only 2.5 mW. Recently, there have been models of DACs of the type discussed above with a higher speed. For example, the 12-bit AD7943 has a settling time of 0.6 μs and a power consumption of only 25 μW. Low intrinsic consumption allows such micropower DACs to be powered directly from the reference voltage source. At the same time, they may not even have a pin for connecting an ION, for example, an AD5321.
DAC on current sources
DACs on current sources have higher accuracy. Unlike the previous version, in which the weight currents are formed by relatively small resistors and, as a result, depend on the resistance of the switches and the load, in this case the weight currents are provided by transistor current sources with high dynamic resistance. A simplified DAC circuit based on current sources is shown in Fig. 6.
Rice. 6. DAC circuit on current sources
Weight currents are generated using a resistive matrix. The base potentials of the transistors are the same, and so that the potentials of the emitters of all transistors are equal, the areas of their emitters are made different in accordance with the weight coefficients. The right matrix resistor is not connected to the common bus, as in the diagram in Fig. 4, and to two parallel connected identical transistors VT 0 and VT n, as a result of which the current through VT 0 is equal to half the current through VT 1. The input voltage for the resistive matrix is created using the reference transistor VT op and the operational amplifier OU1, the output voltage of which is set such that the collector current of the transistor VT op takes the value I op. Output current for N-bit DAC
Typical examples of DACs on current switches with bipolar transistors as switches are the 12-bit 594PA1 with a settling time of 3.5 μs and a linearity error of no more than 0.012% and the 12-bit AD565, which has a settling time of 0.2 μs with the same linearity error. The AD668 is even faster with a 90 ns settling time and the same linearity error. Newer designs include a 14-bit AD9764 with 35 ns settling time and a linearity error of no more than 0.01%. Bipolar differential stages, in which transistors operate in an active mode, are often used as switches for the current S k. This allows the settling time to be reduced to a few nanoseconds. The circuit of the current switch on differential amplifiers is shown in Fig. 7.
Differential stages VT 1 -VT 3 and VT "1 -VT" 3 are formed from standard ECL valves. The current I k flowing through the collector terminal of the output emitter follower is the output current of the cell. If a high level voltage is applied to the digital input D k, then the transistor VT 3 opens, and the transistor VT "3 closes. The output current is determined by the expression
The accuracy increases significantly if the resistor R e is replaced by a constant current source, as in the circuit in Fig. 6. Due to the symmetry of the circuit, it is possible to generate two output currents - direct and inverse. The fastest models of such DACs have ECL input levels. An example is the 12-bit MAX555, which has a settling time of 4 ns to 0.1%. Since the output signals of such DACs capture the radio frequency range, they have an output impedance of 50 or 75 ohms, which must be matched to the characteristic impedance of the cable connected to the output of the converter.
DAC APPLICATION
The use of digital-to-analog converters applies not only to the field of code-to-analog conversion. Using their properties, you can determine the products of two or more signals, build function dividers, analog links controlled from microcontrollers, such as attenuators, integrators. Signal generators, including arbitrary waveforms, are also an important area of DAC application. Some of the signal processing circuits that include D / A converters are discussed below.
Handling signed numbers
Until now, when describing digital-to-analog converters, input digital information was represented in the form of natural numbers (unipolar). The handling of integers (bipolar) has certain peculiarities. Typically binary integers are represented using two's complement code. In this way, using eight digits, you can represent numbers in the range from -128 to +127. When entering numbers into the DAC, this range of numbers is shifted to 0 ... 255 by adding 128. Numbers greater than 128 are considered positive, and numbers less than 128 are negative. Average 128 corresponds to zero. This representation of signed numbers is called offset code. Adding a number that is half the full scale of a given bit depth (in our example, it is 128) can be easily done by inverting the most significant (signed) bit. The correspondence of the considered codes is illustrated in table. one.
Table 1
Relationship between digital and analog values
To obtain the correct signed output signal, you must reverse-shift by subtracting the current or voltage that is half the scale of the transducer. This can be done in different ways for different types of DACs. For example, in a DAC based on current sources, the range of variation of the reference voltage is limited, and the output voltage has the polarity opposite to that of the reference voltage. In this case, the bipolar mode is most easily implemented by connecting an additional bias resistor R cm between the DAC output and the reference voltage input (Fig. 8a). Resistor R cm is made on an IC chip. Its resistance is chosen so that the current I cm is half the maximum value of the DAC output current.
In principle, the problem of output current bias can be solved in a similar way for a DAC based on MOS switches. To do this, you need to invert the reference voltage, and then form a bias current from -U op, which should be subtracted from the DAC output current. However, to maintain thermal stability, it is best to provide bias current generation directly in the DAC. To do this, the circuit in Fig. 8a, a second operational amplifier is introduced and the second DAC output is connected to the input of this op-amp (Fig.8b).
DAC second output current,
At the input of OU1, the current I "out is summed up with the current I mr, which corresponds to the unit of the least significant bit of the input code.
The total current is inverted. The current flowing through the feedback resistor R OS OS2 is
Or 
At 
and at 
In the case of N = 8, up to a factor of 2, it coincides with the data in Table. 6, taking into account the fact that for the converter on MOS switches the maximum output current is
.
If the resistors R 2 are well matched in resistance, then the absolute change in their value with temperature fluctuations does not affect the output voltage of the circuit.
In digital-to-analog converters with an output signal in the form of a voltage, built on an inverse resistive matrix (see Fig. 9), it is easier to implement a bipolar mode (Fig. 8c). Typically, such DACs contain an on-chip output buffer amplifier. To operate the DAC in a unipolar connection, the free output of the lower resistor R according to the scheme is not connected, or connected to a common point of the circuit to double the output voltage. For bipolar operation, the free terminal of this resistor is connected to the DAC reference voltage input. In this case, the op-amp operates in differential connection and its output voltage
As already mentioned above, DAC converters on MOS switches allow a change in the reference voltage over a wide range, including a change in polarity. The DAC output voltage is proportional to the product of the reference voltage and the input digital code. This circumstance makes it possible to directly use such DACs for multiplying an analog signal by a digital code.
When the DAC is unipolar, the output signal is proportional to the product of the bipolar analog signal by the unipolar digital code. Such a multiplier is called two-quadrant. When the DAC is bipolar (Fig. 8b and 8c), the output signal is proportional to the product of the bipolar analog signal by the bipolar digital code. This circuit can operate as a four-quadrant multiplier.
The division of the input voltage by the digital scale M D = D / 2 N is performed using a two-quadrant divider circuit (Fig. 9).
In the diagram in fig. 9a, the converter on MOS switches with a current output operates as a voltage-to-current converter controlled by the D code and included in the OA feedback circuit. The input voltage is applied to the free terminal of the DAC feedback resistor located on the IC chip.
In this circuit, the DAC output current is
,
which under the condition R o = R gives
.
It should be noted that when the code is "all zeros", the feedback is opened. This mode can be prevented either by prohibiting such a code programmatically, or by connecting a resistor with a resistance equal to R · 2 N + 1 between the output and the inverting input of the op-amp.
The divider circuit based on a DAC with an output in the form of a voltage, built on an inverse resistive matrix and including a buffer op-amp, is shown in Fig. 9b. The output and input voltages of this circuit are related by the equation
this implies 
.
In this circuit, the amplifier is covered by both positive and negative feedbacks. For the prevalence of negative feedback (otherwise the op-amp will turn into a comparator), condition D<2 N-1 или M D <1/2. Это ограничивает значение входного кода нижней половиной шкалы.
DAC PARAMETERS
With a sequential increase in the values of the input digital signal D (t) from 0 to 2 N -1 through the unit of the least significant bit (EMP), the output signal U out (t) forms a stepped curve. This dependence is usually called the conversion characteristic of the DAC. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (Fig. 10), which corresponds to the ideal transformation characteristic. The actual transformation characteristic may differ significantly from the ideal in the size and shape of the steps, as well as the location on the coordinate plane. There are a number of parameters to quantify these differences.
Rice. 10 Static characteristic of DAC conversion
Static parameters
Resolution - the increment of U out when converting adjacent values of D j, i.e. differing on EMP. This increment is a quantization step. For binary conversion codes, the nominal value of the quantization step is h = U psh / (2 N -1), where U psh is the nominal maximum output voltage of the DAC (full scale voltage), N is the bit width of the DAC. The larger the digit capacity of the converter, the higher its resolution. Full Scale Accuracy is the relative difference between the real and ideal values of the conversion scale limit in the absence of a zero offset.
.
It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.
Zero offset error - U out value when the DAC input code is zero. It is an additive component of the total error. Usually indicated in millivolts or as a percentage of full scale:
.
Nonlinearity is the maximum deviation of the actual conversion characteristics U out (D) from the optimal one (line 2 in Fig. 10). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Non-linearity is usually defined in relative units, but in the reference data it is also given in the EMP. For the characteristic shown in Fig. 10
.
Differential nonlinearity is the maximum change (taking into account the sign) of the deviation of the real transformation characteristic U out (D) from the optimal one when passing from one value of the input code to another adjacent value. Usually defined in relative units or in EMP. For the characteristic shown in Fig. 10,
.
Monotonicity of the conversion characteristics - an increase (decrease) in the output voltage of the DAC U out with an increase (decrease) in the input code D. If the differential nonlinearity is greater than the relative quantization step h / U psh, then the characteristic of the converter is non-monotonic.
Thermal instability of a digital-to-analog converter is characterized by temperature coefficients of full scale error and zero offset error.
Full scale and zero offset errors can be eliminated by calibration (trim). Nonlinearity errors cannot be eliminated by simple means.
The dynamic parameters of the DAC are determined by the change in the output signal with a jump change in the input code, usually from the value "all zeros" to "all ones" (Fig. 11).
Rice. 11. DAC transient response
The settling time is the time interval from the moment the input code changes (in Fig. 11 t = 0) to the moment when the equality is last fulfilled
| U out -U psh | = d / 2,
where d / 2 usually corresponds to EMP.
The slew rate is the maximum rate of change of U out (t) during the transient process. It is defined as the ratio of the increment DU out to the time Dt, during which this increment occurred. Typically specified in the datasheet for a DAC with a voltage output. For a DAC with a current output, this parameter is largely dependent on the type of output op-amp.
For multiplying DACs with voltage output, unity gain frequency and power bandwidth are often specified, which are mainly determined by the properties of the output amplifier.
LIST OF USED LITERATURE
1. Federkov BG, Taurus VA, DAC and ADC microcircuits: operation, parameters, application. M .: Energoizdat, 1990. –320p.
2. Valakh VV, Grigoriev VF, High-speed ADCs for measuring the shape of random signals M .: Instruments and experimental techniques. 1987. No. 4 p.86-90
3. High-speed integrated circuits DAC and ADC and measurement of their parameters. Edited by Marcinkyavuches. M .: Radio and communication. 1988 -224s. ©
Digital-to-analog converters (DAC) - designed to convert digital signals to analog. Such a conversion is necessary, for example, when restoring an analog signal, previously converted to digital for transmission over a long distance or storage (such a signal, in particular, can be sound). Another example of using such a conversion is obtaining a control signal for digital control of devices, the operating mode of which is determined directly by an analog signal (which, in particular, occurs when controlling motors).
(xtypo_quote) The main parameters of the DAC include resolution, settling time, nonlinearity error, etc. (/ xtypo_quote)
Resolution is the reciprocal of the maximum number of steps for quantizing the analog output signal. Settling time t set - the time interval from the application of the code to the input until the moment when the output signal enters the specified limits, determined by the error. Nonlinearity error is the maximum deviation of the graph of the dependence of the output voltage on the voltage specified by a digital signal with respect to the ideal straight line in the entire conversion range.
Like the ones under consideration, DACs are the "link" between analog and digital electronics. There are various principles for constructing an ADC.
DAC circuit with summation of weight currents
In fig. 3.88 shows the DAC circuit with the summation of the weight currents.
Key S 5 is closed only when all keys S 1 ... S 4 are open (with u out = 0). U 0
- reference voltage. Each resistor in the input circuit corresponds to a specific bit of the binary number.
This DAC is essentially an op-amp-based inverting amplifier. The analysis of such a scheme is not difficult. So, if one key is closed
S1, then u out = −U 0 R oc / R
which corresponds to the first and zeros in the remaining digits.
From the analysis of the circuit, it follows that the output voltage module is proportional to the number, the binary code of which is determined by the state of the keys S 1 ... S 4. The currents of the keys S 1 ... S 4 are summed up at the point "a", and the currents of different keys are different (have different "weight"). This determines the name of the circuit.
From the above it follows that u out = - (U 0 R oc / R) S 1 - (U 0 R oc / (R / 2)) S 2 - - (U 0 R oc / (R / 4)) S 3 - (U 0 R oc / (R / 8)) S 4 = = - (U 0 R oc / R) (8S 4 + 4S 3 + 2S 2 + S 1)
where S i, i = 1, 2, 3, 4 takes on the value 1 if the corresponding key is closed, and 0 if the key is open.
The state of the keys is determined by the input transformed code. The circuit is simple, but it has disadvantages: significant changes in the voltage across the keys and the use of resistors with very different resistances. It is difficult to provide the required accuracy of these resistances.
DAC based on resistive matrix R - 2R
Consider a DAC based on a resistive matrix R - 2R (constant resistance matrix) (Fig. 3.89). 
The circuit uses the so-called changeover keys S 1 ... S 4, each of which in one of the states is connected to a common point, so the voltages on the keys are low. Key S 5 is closed only when all keys S 1 ... S 4 are connected to a common point. The input circuit uses resistors with only two different resistance values.
From the analysis of the circuit, you can see that for it, the output voltage module is proportional to the number, the binary code of which is determined by the state of the keys S 1 ... S 4. The analysis is easy to carry out considering the following. Let each of the keys S 1 ... S 4 be connected to a common point. Then, as it is easy to see, the voltage relative to the common point at each next of the points "a" ... "d" is 2 times greater than in the previous one. For example, the voltage at point "b" is 2 times greater than at point "a" (the voltages U a, U b, U c and U d at these points are determined as follows:
Let's assume that the state of the specified keys has changed. Then the voltages at points "a" ... "d" will not change, since the voltage between the inputs of the operational amplifier is practically zero.
From the above it follows that:
u out = - (U 0 R oc / 2R) S 4 - ((U 0/2) R oc / 2R) S 3 - ((U 0/4) R oc / 2R) S 2 - (( U 0/8) R oc / 2R) S 1 = - (U 0 R oc / 16R) (8S 4 + 4S 3 + 2S 2 + S 1)
where S i, i = 1, 2, 3, 4 takes on the value 1 if the corresponding key is closed, and 0 if the key is open.
DAC for BCD conversion
Consider a digital-to-analog converter (BCD) conversion (Figure 3.90).
A separate matrix R - 2R (indicated by rectangles) is used to represent each digit of the decimal number. Z 0 ... Z 3 denote the numbers determined by the state of the keys of each matrix R - 2R. The principle of operation becomes clear if we take into account that the resistance of each matrix R, and if we analyze the fragment of the circuit shown in Fig. 3.91. 
It follows from the analysis that
U 2 = U 1 · [(R || 9R) / (8,1R + R || 9R)]
R || 9R = (R 9R) / (R + 9R) = 0.9R
Therefore, U 2 = 0.1 U 1. With this in mind, we get
u out = - (U 0 R oc / 16R) 10 −3 (10 3 Z 3 + 10 2 Z 2 + 10 Z 1 + Z 0)
The most common are DACs of 572, 594, 1108, 1118 and others. 3.2 are given ...
Parameters of some DACs
Analog to digital converter(ADC, English Analog-to-digital converter, ADC) - a device that converts an input analog signal into a discrete code (digital signal). The reverse conversion is carried out using a DAC (digital to analogue converter, DAC).
Typically, an ADC is an electronic device that converts voltage into a binary digital code. However, some non-electronic devices with a digital output should also be classified as ADCs, such as some types of angle-to-code converters. The simplest one-bit binary ADC is a comparator.
Permission
ADC resolution - the minimum change in the value of an analog signal that can be converted by a given ADC - is related to its capacity. In the case of a single measurement without taking into account noise, the resolution is directly determined by the ADC capacity.
The ADC capacity characterizes the number of discrete values that the converter can output at the output. In binary ADCs it is measured in bits, in ternary ADCs it is measured in trites. For example, a binary 8-bit ADC is capable of producing 256 discrete values (0 ... 255), since a ternary 8-bit ADC is capable of producing 6561 discrete values, since.
The voltage resolution is equal to the voltage difference corresponding to the maximum and minimum output code divided by the number of discrete output values. For instance:
Input range = 0 to 10 volts
Binary ADC 12 bits: 212 = 4096 quantization levels
Binary ADC voltage resolution: (10-0) / 4096 = 0.00244 volts = 2.44 mV
Bit depth of ternary ADC 12 trit: 312 = 531 441 quantization level
Voltage resolution of ternary ADC: (10-0) / 531441 = 0.0188 mV = 18.8 μV
Input range = -10 to +10 volts
Bit ADC 14 bits: 214 = 16384 quantization levels
Binary ADC voltage resolution: (10 - (- 10)) / 16384 = 20/16384 = 0.00122 volts = 1.22 mV
Bit depth of ternary ADC 14 trit: 314 = 4 782 969 quantization levels
Voltage resolution of ternary ADC: (10 - (- 10)) / 4782969 = 0.00418 mV = 4.18 μV
In practice, the resolution of the ADC is limited by the signal-to-noise ratio of the input signal. With a high noise intensity at the ADC input, it becomes impossible to distinguish adjacent levels of the input signal, that is, the resolution deteriorates. In this case, the actually achievable resolution is described by the effective number of bits (ENOB), which is less than the actual bit depth of the ADC. When converting a highly noisy signal, the least significant bits of the output code are practically useless, since they contain noise. To achieve the declared bit width, the S / N ratio of the input signal should be approximately 6 dB for each bit of bit depth (6 dB corresponds to a fourfold change in the signal level).
Conversion types
According to the method used by the algorithms, the ADC is divided into:
Consecutive forward enumeration
Successive approximation
Serial sigma-delta modulation
Parallel single stage
Parallel two- or more stage (conveyor)
The transfer characteristic of the ADC is the dependence of the numerical equivalent of the output binary code on the value of the input analog signal. They talk about linear and non-linear ADCs. This division is conditional. Both transmission characteristics are stepped. But for "linear" ADCs it is always possible to draw such a straight line so that all points of the transfer characteristic corresponding to the input values delta * 2 ^ k (where delta is the sampling step, k lies in the range 0..N, where N is the ADC bit width) equidistant from it.
Accuracy
There are several sources of ADC error. Quantization errors and (assuming the ADC should be linear) nonlinearities are inherent in any A / D conversion. In addition, there are so-called aperture errors that are a consequence of the jitter of the clock generator, they appear when the signal is converted as a whole (and not just one sample).
These errors are measured in units called LSB - least significant bit. In the above example of an 8-bit binary ADC, an error in 1 LSB is 1/256 of the full signal range, that is, 0.4%, in a 5-bit ternary ADC, an error in 1 LSB is 1/243 of the full signal range, that is 0.412%, in an 8-bit ternary ADC the error in 1 LSM is 1/6561, that is, 0.015%.
ADC types
The following are the main ways to build electronic ADCs:
ADC direct conversion:
Parallel direct-conversion ADCs, completely parallel to the ADCs, contain one comparator for each discrete input level. At any time, only comparators corresponding to levels below the input signal level output an excess signal at their output. Signals from all comparators go either directly to a parallel register, then the code is processed in software, or to a hardware logical encoder that generates the required digital code in hardware, depending on the code at the encoder input. The data from the encoder is recorded in a parallel register. The sampling rate of parallel ADCs generally depends on the hardware characteristics of the analog and logic gates, as well as the required sampling rate.
Parallel direct-conversion ADCs are the fastest, but usually have a resolution of no more than 8 bits, since they entail high hardware costs (comparators). ADCs of this type have a very large chip size, high input capacitance, and can produce short-term output errors. Often used for video or other high frequency signals, and are widely used in industry to monitor rapidly changing processes in real time.
Pipelined ADC operation is used in parallel-to-serial direct-conversion ADCs, in contrast to the normal operation of parallel-serial direct-conversion ADCs, in which data is transmitted after complete conversion, during pipeline operation, partial conversion data is transmitted as soon as it is ready until the complete conversion is completed.
A successive approximation ADC, or bit-balanced ADC, contains a comparator, an auxiliary DAC, and a successive approximation register. The ADC converts an analog signal to a digital one in N steps, where N is the ADC capacity. At each step, one bit of the desired digital value is determined, starting from the NWR and ending with the MWR. The sequence of actions for determining the next bit is as follows. The auxiliary DAC is set to an analog value formed from the bits already defined in the previous steps; the bit to be determined in this step is set to 1, the least significant bits are set to 0. The value obtained on the auxiliary DAC is compared with the input analog value. If the value of the input signal is greater than the value on the auxiliary DAC, then the determined bit is set to 1, otherwise 0. Thus, the determination of the final digital value is like a binary search. ADCs of this type have both high speed and good resolution. However, in the absence of a sample storage device, the error will be much larger (imagine that after digitizing the largest bit, the signal begins to change).
ADCs of differential coding (English delta-encoded ADC) contain a reversing counter, the code from which goes to the auxiliary DAC. The input signal and the signal from the auxiliary DAC are compared on a comparator. Due to negative feedback from the comparator to the counter, the code on the counter is constantly changing so that the signal from the auxiliary DAC differs as little as possible from the input signal. After some time, the difference between the signals becomes less than the LSM, while the counter code is read as the digital output signal of the ADC. ADCs of this type have a very large input signal range and high resolution, but the conversion time depends on the input signal, although it is limited from the top. In the worst case, the conversion time is equal to Tmax = (2q) / fс, where q is the ADC capacity, fс is the counter clock generator frequency. Differential-encoding ADCs are usually a good choice for digitizing real-world signals, since most signals in physical systems are not prone to hopping. Some ADCs use a combined approach: differential coding and successive approximation; this works especially well in cases where the high frequency components in the signal are known to be relatively small.
Ramp comparison ADCs (some ADCs of this type are called Integrating ADCs, also include sequential ADCs) contain a sawtooth voltage generator (in a sequential ADC, a step voltage generator consisting of a counter and a DAC), a comparator and a time counter. The sawtooth waveform rises linearly from low to high, then quickly falls off to low. At the start of the rise, the time counter starts. When the sawtooth signal reaches the input level, the comparator is triggered and stops the counter; the value is read from the counter and fed to the ADC output. This type of ADC is the simplest in structure and contains the minimum number of elements. At the same time, the simplest ADCs of this type have rather low accuracy and are sensitive to temperature and other external parameters. The sawtooth generator can be built around a counter and an auxiliary DAC to increase accuracy, but this structure has no other advantages over successive approximation and differential encoding ADCs.
ADCs with charge balancing (these include ADCs with two-stage integration, ADCs with multi-stage integration, and some others) contain a constant current generator, a comparator, a current integrator, a clock generator, and a pulse counter. The transformation takes place in two stages (two-stage integration). In the first step, the input voltage value is converted into a current (proportional to the input voltage), which is fed to the current integrator, the charge of which is initially zero. This process lasts for TN time, where T is the period of the clock generator, N is a constant (a large integer, which determines the charge accumulation time). After this time, the integrator input is disconnected from the ADC input and connected to the constant current generator. The polarity of the generator is such that it reduces the charge stored in the integrator. The discharge process lasts until the charge in the integrator decreases to zero. Discharge time is measured by counting clock pulses from the moment the discharge starts until zero charge is reached on the integrator. The counted number of clock pulses will be the output code of the ADC. It can be shown that the number of pulses n, counted during the discharge time, is equal to: n = Uin N (RI0) −1, where Uin is the input voltage of the ADC, N is the number of pulses in the accumulation stage (defined above), R is the resistance of the resistor that converts the input voltage into current, I0 is the value of the current from the stable current generator, which discharges the integrator at the second stage. Thus, potentially unstable parameters of the system (first of all, the capacitance of the integrator's capacitor) are not included in the final expression. This is a consequence of the two-stage process: the errors introduced in the first and second stages are mutually subtracted. Even the long-term stability of the clock generator and the comparator bias voltage are not imposed: these parameters must be stable only for a short time, that is, during each conversion (no more than 2TN). In fact, the principle of two-stage integration allows you to directly convert the ratio of two analog quantities (input and reference current) to the ratio of numeric codes (n and N in terms defined above) with little or no additional error. Typical ADCs of this type are 10 to 18 bits wide. An additional advantage is the ability to build converters that are insensitive to periodic interference (for example, interference from the mains supply) due to accurate integration of the input signal over a fixed time interval. The disadvantage of this type of ADC is its low conversion speed. Charge-balanced ADCs are used in high-precision measuring instruments.
ADC with intermediate conversion to pulse repetition rate. The signal from the sensor passes through a level converter and then through a voltage-to-frequency converter. Thus, a signal is sent directly to the input of the logic circuit, the characteristic of which is only the frequency of the pulses. The logical counter accepts these pulses as input during the sampling time, thus giving out to its end a code combination, numerically equal to the number of pulses that arrived at the converter during the sampling time. Such ADCs are quite slow and not very accurate, but nevertheless they are very simple to implement and therefore have a low cost.
Sigma-delta-ADC (also called delta-sigma ADC) performs analog-to-digital conversion with a sampling rate many times higher than the required one and, by filtering, leaves only the required spectral band in the signal.
Non-electronic ADCs are usually built on the same principles.
Commercial ADCs
As a rule, they are produced in the form of microcircuits.
For most ADCs, the bit width is from 6 to 24 bits, the sampling rate is up to 1 MHz. Mega and gigahertz ADCs are also available (February 2002). Megahertz ADCs are required in digital video cameras, video capture devices, and digital TV tuners to digitize the composite video signal. Commercial ADCs typically have an output error of ± 0.5 to ± 1.5 LSB.
One of the factors that add to the cost of ICs is the number of pins, since they force the package to be made larger and each pin must be connected to a die. To reduce the number of pins, often ADCs operating at low sample rates have a serial interface. Serial ADCs are often used to increase wiring density and create a smaller board.
Often ADC microcircuits have several analog inputs connected inside the microcircuit to a single ADC through an analog multiplexer. Various ADC models may include sample-hold devices, instrumentation amplifiers or high-voltage differential input, and other similar circuits.
Other applications
Analog-to-digital conversion is used wherever it is required to receive an analog signal and process it digitally.
Special video ADCs are used in computer TV tuners, video input cards, and video cameras to digitize the video signal. Microphone and line audio inputs of computers are connected to audio-ADC.
ADCs are an integral part of data acquisition systems.
8-12 bit successive approximation ADC and 16-24 bit sigma-delta ADC are built into single-chip microcontrollers.
Very fast ADCs are needed in digital oscilloscopes (parallel and pipelined ADCs are used)
Modern balances use ADCs up to 24 bits, which convert the signal directly from a strain gauge sensor (sigma-delta-ADC).
ADCs are part of radio modems and other radio data transmission devices, where they are used in conjunction with a DSP processor as a demodulator.
Ultrafast ADCs are used in base station antenna systems (so-called SMART antennas) and in radar antenna arrays.
Digital-to-analog converter (DAC) - a device for converting a digital (usually binary) code into an analog signal (current, voltage or charge). D / A converters are the interface between the discrete digital world and analog signals.
An analog-to-digital converter (ADC) performs the opposite operation.
An audio DAC usually receives a digital signal at its input in pulse-code modulation (PCM, pulse-code modulation). The task of converting various compressed formats to PCM is handled by the appropriate codecs.
Application
The DAC is always used when it is necessary to convert a signal from digital to analog, for example, in CD players (Audio CD).
DAC types
The most common types of electronic DACs are:
A pulse width modulator is the simplest type of DAC. A stable current or voltage source is periodically switched on for a time proportional to the converted digital code, then the resulting pulse sequence is filtered by an analog low-pass filter. This method is often used to control the speed of electric motors, and is also becoming popular in Hi-Fi audio equipment;
Oversampling DACs, such as sigma-delta DACs, are based on variable pulse density. Oversampling allows using a DAC with a lower bit depth to achieve a higher bit depth of the final conversion; often delta-sigma DACs are based on the simplest 1-bit DAC that is nearly linear. A low-bit DAC receives a pulse signal with a modulated pulse density (with a constant pulse width, but with a variable duty cycle), created using negative feedback. Negative feedback acts as a high-pass filter for quantization noise.
Most high-capacity DACs (over 16 bits) are built on this principle due to its high linearity and low cost. Delta-sigma DAC performance reaches hundreds of thousands of samples per second, bit depth - up to 24 bits. A simple first-order or higher-order delta-sigma modulator such as MASH (Multi stage noise SHaping) can be used to generate a pulse density modulated signal. As the oversampling rate increases, the requirements for the output low-pass filter are softened and the suppression of quantization noise improves;
A weighing type DAC, in which each bit of the converted binary code corresponds to a resistor or current source connected to a common summation point. The source current (resistor conductance) is proportional to the weight of the bit to which it corresponds. Thus, all non-zero bits of the code are added to the weight. The weighting method is one of the fastest, but it is characterized by low accuracy due to the need for a set of many different precision sources or resistors and variable impedance. For this reason, weighting DACs are no more than eight bits wide;
Ladder DAC (R-2R chain circuit). In the R-2R-DAC, the values are created in a special circuit consisting of resistors with resistances R and 2R, called a constant impedance matrix, which has two types of switching: direct - a matrix of currents and inverse - a matrix of voltages. The use of the same resistors can significantly improve the accuracy compared to a conventional weighing DAC, since it is relatively easy to manufacture a set of precision elements with the same parameters. DACs of the R-2R type allow to push back the restrictions on the bit width. With laser trimmed resistors on a single substrate, an accuracy of 20-22 bits is achieved. Most of the conversion time is spent in the operational amplifier, so it should have maximum performance. DAC speed of a few microseconds or less (i.e. nanoseconds);
SpecificationsDACs are located at the beginning of the analog path of any system, therefore the DAC parameters largely determine the parameters of the entire system as a whole. The following are the most important characteristics of a DAC.
Bit depth is the number of different output signal levels that the DAC can reproduce. Usually given in bits; the number of bits is the base 2 logarithm of the number of levels. For example, a one-bit DAC is capable of reproducing two () levels, and an eight-bit DAC is capable of playing 256 () levels. The bit depth is closely related to the effective bit depth (ENOB, Effective Number of Bits), which shows the real resolution attainable on a given DAC.
The maximum sampling rate is the maximum frequency at which the DAC can operate to produce the correct output. In accordance with the Nyquist - Shannon theorem (also known as the Kotelnikov theorem), for the correct reproduction of an analog signal from a digital form, it is necessary that the sampling frequency be at least twice the maximum frequency in the signal spectrum. For example, to reproduce the entire human-audible audio frequency range, the spectrum of which extends up to 20 kHz, it is necessary that the audio signal be sampled with a frequency of at least 40 kHz. The Audio CD standard sets the audio sampling rate to 44.1 kHz; to reproduce this signal, you need a DAC capable of operating at this frequency. In cheap computer sound cards, the sampling rate is 48 kHz. Signals sampled at other frequencies are oversampled up to 48 kHz, which partially degrades the signal quality.
Monotony is the property of a DAC to increase the analog output signal as the input code increases.
THD + N (Total Harmonic Distortion + Noise) is a measure of the distortion and noise introduced into the signal by the DAC. Expressed as a percentage of harmonic power and noise in the output signal. An important parameter for small-signal DAC applications.
Dynamic range is the ratio of the largest to the smallest signal that the DAC can reproduce, expressed in decibels. This parameter is related to bit width and noise threshold.
Static characteristics:
DNL (differential nonlinearity) - characterizes how the increment of the analog signal, obtained when the code is increased by 1 least significant bit (LSB), differs from the correct value;
INL (integral non-linearity) - characterizes how much the transfer characteristic of the DAC differs from the ideal. The ideal characteristic is strictly linear; INL shows how much the voltage at the DAC output for a given code is from the linear characteristic; expressed in minimum wage;
gain;
bias.
Frequency characteristics:
SNDR (signal-to-noise ratio + distortion) - characterizes in decibels the ratio of the output signal power to the total power of noise and harmonic distortion;
HDi (coefficient of the i-th harmonic) - characterizes the ratio of the i-th harmonic to the fundamental harmonic;
THD (Total Harmonic Distortion) - the ratio of the total power of all harmonics (except the first) to the power of the first harmonic
D / A converters have static and dynamic characteristics.
DAC static characteristics
The main static characteristics DACs are:
· resolution;
· Nonlinearity;
· Differential nonlinearity;
· Monotony;
· Conversion factor;
· Absolute errors of the full scale;
· Relative errors of the full scale;
· Zero offset;
Absolute error
Resolution Is the increment U OUT when converting adjacent values of D j, i.e. differing by one least significant digit (EMP). This increment is a quantization step. For binary transform codes, the nominal value of the quantization step is
h = U PSh / (2 N - 1),
where U ПШ is the nominal maximum output voltage of the DAC (full scale voltage), N is the capacity of the DAC. The larger the digit capacity of the converter, the higher its resolution.
Full Scale Accuracy - the relative difference between the real and ideal values of the conversion scale limit in the absence of a zero offset, i.e.
It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.
Zero offset error - the value of U OUT when the input code of the DAC is zero. It is an additive component of the total error. Usually indicated in millivolts or as a percentage of full scale:
Non-linearity - the maximum deviation of the actual conversion characteristics U OUT (D) from the optimal one (Fig. 5.2, line 2). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Non-linearity is usually defined in relative units, but in the reference data it is also given in the EMP. For the characteristic shown in Fig. 5.2,
Differential nonlinearity - the maximum change (taking into account the sign) of the deviation of the real conversion characteristic U OUT (D) from the optimal one when passing from one value of the input code to another adjacent value. Usually defined in relative units or in EMP. For the characteristic shown in Fig. 5.2,
Monotone conversion characteristics - an increase (decrease) in the output voltage of the DAC (U OUT) with an increase (decrease) in the input code D... If the differential nonlinearity is greater than the relative quantization step h / U PN, then the transducer characteristic is non-monotonic.
Temperature instability of the DAC is characterized by temperature coefficients full scale errors and zero offset errors.
Full scale and zero offset errors can be eliminated by calibration (trim). Nonlinearity errors cannot be eliminated by simple means.
DAC dynamic characteristics
TO dynamic characteristics am DACs include settling time and conversion time.
With a sequential increase in the values of the input digital signal D (t) from 0 to (2 N - 1) through the unit of the least significant bit, the output signal U OUT (t) forms a stepped curve. This dependence is usually called the conversion characteristic of the DAC. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (see Fig. 5.2), which corresponds to the ideal transformation characteristic. The actual transformation characteristic may differ significantly from the ideal in the size and shape of the steps, as well as the location on the coordinate plane. There are a number of parameters to quantify these differences.
The dynamic parameters of the DAC are determined by the change in the output signal with a jump change in the input code, usually from the value "all zeros" to "all ones" (Fig. 5.3).
Settling time
- time interval from the moment of change
input code (Fig.5.3, t = 0) until the last time the equality is executed:
| U OUT - U PSH | = d / 2,
where d / 2 usually corresponds to EMP.
Slew rate - the maximum rate of change U OUT (t) during the transient process. Defined as the ratio of the increment D U OUT to the time Dt during which this increment occurred. Typically specified in the datasheet for a DAC with a voltage output. For digital-to-analog converters with a current output, this parameter is highly dependent on the type of output op-amp.
For multiplying DACs with voltage output, unity gain frequency and power bandwidth are often specified, which are mainly determined by the properties of the output amplifier.
Figure 5.4 shows two methods of linearization, from which it follows that the method of linearization to obtain the minimum value of D l, shown in Fig. 5.4, b, allows to reduce the error D l by half in comparison with the method of linearization by boundary points (Fig. 5.4, a).
For digital-to-analog converters with n binary digits, in the ideal case (in the absence of conversion errors), the analog output U OUT is related to the input binary number as follows:
U OUT = U OP (a 1 2 -1 + a 2 2 -2 + ... + a n 2 -n),
where U OP is the reference voltage of the DAC (from a built-in or external source).
Since ∑ 2 -i = 1 - 2 -n, then with all the bits on, the output voltage of the DAC is:
U OUT (a 1 ... a n) = U OP (1 - 2 -n) = (U OP / 2 n) (2 n - 1) = D (2 n - 1) = U PS,
where U ПШ - full scale voltage.
Thus, when all the bits are turned on, the output voltage of the digital-to-analog converter, which in this case forms U PN, differs from the value of the reference voltage (U OP) by the value of the least significant bit of the converter (D), defined as
D = U OP / 2 n.
When any i-th bit is turned on, the output voltage of the DAC is determined from the ratio:
U OUT / a i = U OP 2 -i.
The digital-to-analog converter converts the digital binary code Q 4 Q 3 Q 2 Q 1 into an analog value, usually the voltage U OUT. or current I OUT. Each bit of the binary code has a certain weight of the i-th bit twice as much as the weight of the (i-1) -th. DAC operation can be described by the following formula:
U OUT = e (Q 1 1 + Q 2 2 + Q 3 4 + Q 4 8 + ...),
where e is the voltage corresponding to the weight of the least significant bit, Q i is the value of the i -th bit of the binary code (0 or 1).
For example, the number 1001 corresponds to:
U OUT = e (1· 1 + 0 · 2 + 0 · 4 + 1 · = 9 · e,
on the number 1100 corresponds to
U OUT = e (0· 1 + 0 · 2 + 1 · 4 + 1 · = 12 · e.
A digital-to-analog converter (DAC) is a device for converting a digital code into an analog signal in proportion to the value of the code.
DACs are used to connect digital control systems with devices that are controlled by the level of an analog signal. Also, DAC is an integral part in many structures of analog-to-digital devices and converters.
The DAC is characterized by a conversion function. It associates a change in a digital code with a change in voltage or current. The DAC conversion function is expressed as follows
U out- the value of the output voltage corresponding to the digital code N in supplied to the DAC inputs.
U max- the maximum output voltage corresponding to the application of the maximum code to the inputs N max
The value To dac, defined by the ratio, is called the digital-to-analog conversion coefficient. Despite the stepped form of the characteristic associated with a discrete change in the input value (digital code), it is believed that DACs are linear converters.
If the value N in represent through the values of the weights of its digits, the transformation function can be expressed as follows
, where
i- bit number of the input code N in; A i- meaning i-th digit (zero or one); U i - weight i-th category; n is the number of bits of the input code (the number of DAC bits).
The discharge weight is determined for a specific bit depth, and is calculated using the following formula
U OP - DAC reference voltage
The principle of operation of most DACs is the summation of the fraction of analog signals (bit weight), depending on the input code.
The DAC can be implemented by summing currents, summing voltages, and dividing voltages. In the first and second cases, in accordance with the values of the bits of the input code, the signals of the generators of currents and sources of EMF are summed up. The latter is a code controlled voltage divider. The last two methods are not widely used due to the practical difficulties of their implementation.
Methods for implementing a DAC with weighted summation of currents
Consider the construction of the simplest DAC with weighted summation of currents.
This DAC consists of a set of resistors and a set of switches. The number of keys and the number of resistors is equal to the number of bits n input code. The resistor values are selected in accordance with the binary law. If R = 3 ohms, then 2R = 6 ohms, 4R = 12 ohms, and so on, i.e. each subsequent resistor is 2 times larger than the previous one. When a voltage source is connected and the keys are closed, a current will flow through each resistor. The values of the currents across the resistors, due to the appropriate choice of their ratings, will also be distributed according to the binary law. When submitting the input code N in the keys are switched on in accordance with the value of the corresponding bits of the input code. The key is closed if the corresponding digit is equal to one. In this case, currents proportional to the weights of these discharges are summed up in the node, and the value of the current flowing from the node as a whole will be proportional to the value of the input code N in.
The resistance of the matrix resistors is chosen quite large (tens of kΩ). Therefore, for most practical cases, the DAC plays the role of a current source for the load. If it is necessary to obtain a voltage at the output of the converter, then a current-voltage converter is installed at the output of such a DAC, for example, on an operational amplifier
However, when the code is changed at the DAC inputs, the amount of current drawn from the reference voltage source changes. This is the main disadvantage of this method of building a DAC. . This construction method can only be used if the voltage reference will be with a low internal resistance. In another case, at the moment of changing the input code, the current taken from the source changes, which leads to a change in the voltage drop across its internal resistance and, in turn, to an additional change in the output current not directly related to the change of the code. This drawback can be eliminated by the structure of the DAC with switching keys.
This structure has two output nodes. Depending on the value of the bits of the input code, the keys corresponding to them are connected to the node associated with the output of the device, or to another node, which is most often grounded. In this case, through each resistor of the matrix, the current flows constantly, regardless of the position of the key, and the amount of current consumed from the reference voltage source is constant.
A common disadvantage of both structures considered is the large ratio between the smallest and largest values of the matrix resistors. At the same time, despite the large difference in resistor ratings, it is necessary to ensure the same absolute accuracy of fitting both the largest and the smallest resistor. In the integrated version of the DAC with the number of digits more than 10, it is rather difficult to provide it.
Structures based on resistive R-2R matrices
With this construction of the resistive matrix, the current in each subsequent parallel branch is two times less than in the previous one. The presence of only two resistors in the matrix makes it quite easy to adjust their values.
The output current for each of the presented structures is proportional simultaneously not only to the value of the input code, but also to the value of the reference voltage. It is often said to be proportional to the product of the two. Therefore, such DACs are called multiplying. Such properties will be possessed by all DAC, in which the formation of the weighted values of the currents corresponding to the weights of the discharges is carried out using resistive matrices.
In addition to their intended use, multiplying DACs are used as analog-to-digital multipliers, as code-controlled resistances and conductivities. They are widely used as building blocks for code-controlled (tunable) amplifiers, filters, reference voltage sources, signal conditioners, etc.
Basic parameters and errors of the DAC
The main parameters that can be seen in the reference:
1. Number of bits - the number of bits of the input code.
2. Conversion factor is the ratio of the output signal increment to the input signal increment for a linear conversion function.
3. The settling time of the output voltage or current is the time interval from the moment of a given code change at the DAC input to the moment at which the output voltage or current will finally enter the zone with the width of the least significant bit ( MHR).
4. Maximum conversion frequency - the highest code change frequency at which the specified parameters correspond to the established standards.
There are other parameters that characterize the performance of the DAC and the features of its functioning. Among them: input voltage of low and high level, current consumption, range of output voltage or current.
The most important parameters for a DAC are those that determine its accuracy characteristics.
Accuracy characteristics of each DAC , first of all, they are determined by the normalized errors.
Errors are divided into dynamic and static. Static errors are errors that remain after the completion of all transient processes associated with a change in the input code. Dynamic errors are determined by transient processes at the DAC output that arose as a result of a change in the input code.
The main types of DAC static errors are:
The absolute conversion error at the end point of the scale is the deviation of the output voltage (current) value from the nominal value corresponding to the end point of the scale of the conversion function. Measured in units of the least significant bit of conversion.
Output zero offset voltage - DC voltage at the output of the DAC with the input code corresponding to the zero value of the output voltage. Measured in units of the least significant digit. Conversion factor error (scale) - associated with the deviation of the slope of the conversion function from the required one.
DAC nonlinearity is the deviation of the actual conversion function from the specified straight line. It is the worst error with which it is difficult to fight.
In general, nonlinearity errors are divided into two types - integral and differential.
Integral nonlinearity error is the maximum deviation of the real characteristic from the ideal one. In fact, the averaged conversion function is considered. Determine this error as a percentage of the final range of the output quantity.
Differential nonlinearity is associated with inaccuracy in setting the bit weights, i.e. with errors of divider elements, scatter of residual parameters of key elements, current generators, etc.
Methods for identification and correction of DAC errors
It is desirable that the error correction is carried out during the manufacture of the transducers (technological adjustment). However, it is often desirable when using a specific sample. BIS in a particular device. In this case, the correction is carried out by introducing into the structure of the device, in addition to LSI DAC additional elements. Such methods are called structural.
The most difficult process is ensuring linearity, since they are determined by the related parameters of many elements and nodes. Most often, only the zero offset, the coefficient
The accuracy parameters provided by technological methods deteriorate when the converter is exposed to various destabilizing factors, first of all, temperature. It is necessary to remember about the aging factor of the elements.
Zero offset and scale errors are easily corrected at the DAC output. To do this, a constant bias is introduced into the output signal, which compensates for the offset of the transducer characteristic. The required conversion scale is set, either by correcting the gain set at the output of the amplifier converter, or by adjusting the value of the reference voltage, if the DAC is a multiplying one.
Test control correction methods consist in identifying the DAC errors over the entire set of permissible input influences and adding corrections calculated on the basis of this to the input or output value to compensate for these errors.
With any correction method with control by a test signal, the following actions are provided:
1. Measurement of the characteristics of the DAC on a set of test influences sufficient to identify errors.
2. Identification of errors by calculating their deviations from the measurement results.
3. Calculation of corrective corrections for the converted values or the required corrective actions on the corrected blocks.
4. Correction.
The control can be carried out once before installing the transducer in the device using special laboratory measuring equipment. It can also be carried out using specialized equipment built into the device. In this case, control, as a rule, is carried out periodically, all the time until the converter is directly involved in the operation of the device. Such an organization of control and correction of the transducers can be carried out during its operation as part of a microprocessor-based measuring system.
The main disadvantage of any end-to-end inspection method is the long inspection time along with the heterogeneity and the large volume of equipment used.
The values of the corrections determined in one way or another are stored, as a rule, in digital form. Correction of errors, taking into account these corrections, can be carried out both in analog and digital form.
With digital correction, corrections are added taking into account their sign to the input code of the DAC. As a result, a code is sent to the DAC input, at which the required voltage or current value is formed at its output. The simplest implementation of this correction method consists of an adjustable DAC, at the input of which a digital storage device is installed ( Memory)... The input code plays the role of an address code. V Memory at the corresponding addresses, the values of the codes supplied to the corrected DAC, calculated in advance, taking into account the amendments, are entered.
For analog correction, in addition to the main DAC, one additional DAC is used. The range of its output signal corresponds to the maximum value of the error of the corrected DAC. The input code is simultaneously fed to the inputs of the corrected DAC and to the address inputs Memory amendments. From Memory correction, the correction corresponding to the given value of the input code is selected. The correction code is converted into a signal proportional to it, which is added to the output signal of the corrected DAC. Due to the smallness of the required range of the output signal of the additional DAC in comparison with the range of the output signal of the corrected DAC, the inherent errors of the first are neglected.
In some cases, it becomes necessary to correct the dynamics of the DAC operation.
The transient response of the DAC when changing different code combinations will be different, in other words - the settling time of the output signal will be different. Therefore, when using a DAC, the maximum settling time must be considered. However, in some cases it is possible to correct the behavior of the transfer characteristic.
Features of the use of LSI DAC
For the successful application of modern BIS It is not enough for a DAC to know the list of their main characteristics and the basic schemes for their inclusion.
Significant effect on application results BIS The DAC fulfills the operational requirements due to the characteristics of a particular microcircuit. These requirements include not only the use of permissible input signals, power supply voltages, capacitance and load resistance, but also the execution of the order of switching on different power supplies, separation of the connection circuits for different power supplies and the common bus, the use of filters, etc.
For precision DACs, the noise output voltage is of particular importance. The peculiarity of the noise problem in the DAC is the presence of voltage surges at its output, caused by switching keys inside the converter. In amplitude, these bursts can reach several tens of weights. MHR and create difficulties in the operation of analog signal processing devices following the DAC. The solution to the problem of suppressing such bursts is to use sample-and-hold devices at the DAC output ( UVH). UVH controlled by the digital part of the system, which forms new code combinations at the DAC input. Before feeding a new code combination UVH is put into storage mode, opening the analog signal transmission circuit to the output. This prevents the DAC output voltage spike from being sent to the pin. UVH, which is then put into tracking mode, repeating the output of the DAC.
Special care when building a DAC based on BIS it is necessary to pay attention to the choice of the operational amplifier, which serves to convert the DAC output current into voltage. When supplying the input code of the DAC at the output OU there will be an error DU due to its bias voltage and equal to
,
where U cm- bias voltage OU; R os- the value of resistance in the feedback circuit OU; R m- the resistance of the resistive matrix of the DAC (output resistance of the DAC), depending on the value of the code applied to its input.
Since the ratio changes from 1 to 0, the error due to U cm, changes in the aisles (1 ... 2) U cm... Influence U cm neglected when using OU, which one .
Due to the large area of transistor switches in CMOS BIS significant output capacitance of the LSI DAC (40 ... 120 pF depending on the value of the input code). This capacitance has a significant effect on the settling time of the output voltage. OU to the required accuracy. To reduce this influence R os shunted by a capacitor With wasps.
In some cases, a bipolar output voltage must be obtained at the DAC output. This can be achieved by introducing an offset of the output voltage range at the output, and for multiplying DACs by switching the polarity of the reference voltage source.
Please note that if you are using an integrated DAC , having the number of bits more than you need, then the inputs of unused bits are connected to the ground bus, unambiguously determining the logic zero level on them. Moreover, in order to work as possible with a large range of the output signal of the LSI DAC for such digits, the digits are taken, starting with the least significant one.
One of the practical examples of DAC applications are signal conditioners of various shapes. Made a small model in the proteus. With the help of a DAC of a controlled MK (Atmega8, although it can be done on Tiny), signals of various shapes are generated. The program is written in C in CVAVR. By pressing the button, the generated signal changes.
LSI DAC DAC0808 National Semiconductor, 8-bit, high-speed, included as per typical diagram. Since its output is current, it is converted into voltage with the help of an inverting amplifier on an op-amp.
In principle, you can even have such interesting figures, does something resemble the truth? If you choose a bit more, you get smoother
Bibliography:
1. Bakhtiyarov G.D., Malinin V.V., Shkolin V.P. Analog-to-digital converters / Ed. GD Bakhtiyarova - M .: Sov. radio. - 1980 .-- 278 p .: ill.
2. Design of analog-digital control microprocessor systems.
3.O.V. Shishov. - Saransk: Publishing house of Mordovs. University 1995. - p.
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